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| intel ? ixf1002 dual port gigabit ethernet controller datasheet product features the intel ? ixf1002 dual port gigabit ethernet media access controller (mac), provides two independent 1000 mb/s intelligent, high-performance media access control (mac) ports. it includes gigabit physical coding sublayer (gpcs) interface network management support and is optimized for switch applications. integration ? offers two independent ethernet 1000 mb/s mac ports ? includes gpcs functions for 1000base-x connections ? handles snmp and rmon counters ix bus ? supports up to 5.12 gbps memory bus bandwidth ? variable bus speed of 33 mhz to 80 mhz ? 64-bit bus with three modes of operation: full ? 64 bits for transmit or receive split ? 32 low bits for receive, and 32 high bits for transmit narrow ? 32 bits for transmit or receive ? independent 2 kbyte transmit fifo and 4 kbyte receive fifo for each port ? supports little or big endian byte ordering ? supports receive packet fragmentation on byte boundaries (replay feature) ? programmable transmit and receive bus thresholds ? enables optional appending of packet status performance ? packet transfers are completed prior to servicing cpu interrupt requests ? enables early address filtering ability, with packet header preprocessing ? ieee p802.1q virtual bridged local area network (vlan) tag append, strip and replace function on chip, during packet transmission ? offers ignore or stop transmission options following packet transmission errors ? provides programmable automatic discard of badly received packets such as cyclic redundancy (crc) errors and too long packets ? informs the system in case bad packets start to appear on the fifo bus ? allows interpacket gap (ipg) programming serial ? enables independent mode of operation in each port ? supports ieee 802.3x standard flow-control functionality ? interfaces standard gpcs connections (10b interface) ? interfaces standard gmii connections ? supports 1000base-sx, 1000base-lx, 1000base-cx, and 1000base-t connections ? provides programmable crc generation and removal ? supports auto-negotiation link protocol for 1000base-x ? implements only full-duplex operation ? complies with ieee 802.3z standard ? supports large packets of up to 64 kbytes cpu interface ? supports fully programmable independent ports through a dedicated generic cpu port ? supports interrupt programming ? provides an 8- or 16-bit bus for register access device ? cpu and fifo interfaces are compatible with the ixf440 multiport 10/100 mbps ethernet controller and the ixp1200 network processor. ? includes internal and external loopback capabilities ? provides software reset support ? supports jtag boundary scan ? implemented in a low-power 3.3 v and 5 v tolerant cmos device ? 304-esbga package. order number: 278310-008 june, 2002 notice: this document contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
intel ? ixf1002 dual port gigabit ethernet controller datasheet revision history date revision description 8/31/99 001 initial release. 12/15/99 002 format revision, electrical specification updates. 5/26/00 003 updates for ixp1200 v1.0 release. 9/26/00 004 changed to intel branding with updates for ixp1200 v1.1 release. 12/13/00 005 updates for ixp1200 v1.2 release. 05/18/01 006 updates for the v1.3 sdk. 10/02/01 007 changes to table 16, table 18, section 9.0, figure 56. 5/23/02 008 change to figure 31; removed extended temperature qdf references; added footnote to table 5. information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ? reserved ? or ? undefined. ? intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the ixf1002 may contain design defects or errors known as errata which may cause the product to deviate from published specific ations. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2002 intel is a registered trademark of intel corporation or its subsidiaries in the united states and other countries *other names and brands may be claimed as the property of others. datasheet iii intel ? ixf1002 dual port gigabit ethernet controller contents 1.0 introduction................................................................................................................ ......... 9 1.1 general description............................................................................................... 9 1.2 block diagram ....................................................................................................... 9 1.3 hardware overview.............................................................................................10 2.0 pinout ...................................................................................................................... .........11 2.1 signal description ...............................................................................................11 2.2 pin count.............................................................................................................17 2.3 connection rules ................................................................................................17 2.4 pin list.................................................................................................................18 3.0 registers description ....................................................................................................... 21 3.1 register conventions ..........................................................................................21 3.1.1 access rules..........................................................................................21 3.2 csr register ......................................................................................................22 3.2.1 register mapping ...................................................................................22 3.2.2 base registers .......................................................................................23 3.2.2.1 interrupt status register ...........................................................23 3.2.2.2 interrupt enable register ..........................................................24 3.2.2.3 port control register .................................................................24 3.2.2.4 identification and revision register ..........................................26 3.2.2.5 transmit and receive status register ......................................26 3.2.2.6 transmit counter overflow status register ..............................27 3.2.2.7 receive counter overflow status register ...............................28 3.2.3 configuration registers..........................................................................30 3.2.3.1 transmit and receive error mode register ..............................30 3.2.3.2 fifo threshold register ...........................................................31 3.2.3.3 port working mode register .....................................................32 3.2.3.4 transmit and receive parameters register .............................34 3.2.3.5 transmit threshold register .....................................................35 3.2.3.6 transmit flow-control pause time register ............................35 3.2.3.7 maximum packet size register ................................................37 3.2.3.8 inter packet gap value register ...............................................37 3.2.3.9 mac address registers ............................................................38 3.2.3.10vlan tag length/type register ..............................................38 3.2.3.11transmit counter overflow mask register ...............................39 3.2.3.12receive counter overflow mask register ................................41 3.2.4 gmii management access registers.....................................................42 3.2.4.1 gmii management access register..........................................42 3.2.4.2 gmii management data register..............................................44 3.2.5 gmii management register set.............................................................45 3.2.5.1 gmii control register................................................................45 3.2.5.2 gmii status register .................................................................46 3.2.5.3 an advertisement register .......................................................48 3.2.5.4 an link partner ability base page register .............................49 3.2.5.5 an expansion register .............................................................50 3.2.5.6 an next page register .............................................................51 3.2.5.7 an link partner receive next page register ...........................52 intel ? ixf1002 dual port gigabit ethernet controller iv datasheet 3.2.5.8 extended status register.......................................................... 53 3.2.5.9 gpcs status register............................................................... 54 3.3 network statistic counter mapping..................................................................... 55 3.3.1 register mapping ................................................................................... 55 3.3.2 network statistic counters access rules .............................................. 57 3.4 access sequences.............................................................................................. 57 3.4.1 initialization sequence ........................................................................... 57 3.4.2 mode change sequence ....................................................................... 57 3.4.3 interrupt handling sequence ................................................................. 58 4.0 ix bus interface operation............................................................................................... 59 4.1 ix bus interface................................................................................................... 59 4.1.1 ix bus operating modes ........................................................................ 59 4.1.1.1 signal naming in full-64 and narrow mode.............................. 59 4.1.1.2 signal naming in split mode ..................................................... 59 4.1.2 byte ordering on ix bus ........................................................................ 60 4.1.3 fifo status signaling ............................................................................ 62 4.2 packet transmission........................................................................................... 62 4.2.1 packet loading ...................................................................................... 62 4.2.2 vlan tagging........................................................................................ 63 4.2.2.1 vlan tag functions in ixf1002............................................... 64 4.2.2.2 vlan tag append .................................................................... 64 4.2.2.3 vlan tag strip ......................................................................... 65 4.2.2.4 vlan tag replace.................................................................... 66 4.2.3 network transmission............................................................................ 66 4.2.4 fifo underflow ...................................................................................... 66 4.2.4.1 stopping mode on transmission underflow error..................... 67 4.2.5 transmit flow diagram .......................................................................... 67 4.3 packet reception ................................................................................................ 68 4.3.1 packet storing........................................................................................ 68 4.3.1.1 packet status ............................................................................ 69 4.3.2 header preprocessing ........................................................................... 69 4.3.3 packet segmentation ............................................................................. 70 4.3.4 packet abortion ...................................................................................... 71 4.3.5 network reception................................................................................. 71 4.3.6 rejecting mode on reception errors ..................................................... 71 4.3.7 accepting mode on reception errors..................................................... 71 4.3.8 receive flow diagram ........................................................................... 72 5.0 cpu interface operation.................................................................................................. 73 5.1 cpu interface...................................................................................................... 73 5.2 network management ......................................................................................... 73 5.2.1 snmp mib support................................................................................ 74 5.2.2 rmon statistic group support .............................................................. 74 5.2.3 rmon host group support ................................................................... 75 6.0 network interface operation ............................................................................................ 77 6.1 operating modes................................................................................................. 77 6.2 gmii port interface.............................................................................................. 78 6.3 mac frame format ............................................................................................ 79 6.4 mac transmit operation .................................................................................... 80 datasheet v intel ? ixf1002 dual port gigabit ethernet controller 6.4.1 transmit initiation ...................................................................................80 6.4.2 inter packet gap ....................................................................................80 6.4.3 frame encapsulation .............................................................................80 6.4.4 terminating transmission ......................................................................80 6.4.5 flow control ...........................................................................................81 6.4.5.1 additional flow-control mode ...................................................81 6.5 mac receive operation......................................................................................82 6.5.1 receive initiation ....................................................................................82 6.5.2 preamble processing .............................................................................82 6.5.3 frame decapsulation .............................................................................82 6.5.4 terminating reception ...........................................................................82 6.5.5 flow control ...........................................................................................83 6.6 mac loopback operations .................................................................................83 6.6.1 internal loopback mode.........................................................................83 6.6.2 external loopback mode........................................................................84 6.7 gpcs mode ........................................................................................................84 6.7.1 synchronization......................................................................................86 6.7.1.1 comma detect ...........................................................................86 6.7.2 auto-negotiation.....................................................................................86 7.0 timing diagrams ............................................................................................................. .87 7.1 ix bus port timing diagrams ..............................................................................87 7.1.1 transmit start-of-packet timing.............................................................87 7.1.2 transmit end-of-packet timing..............................................................88 7.1.3 transmit packet timing in split mode....................................................88 7.1.4 transmit packet with vlan tag append timing ...................................89 7.1.5 vlan strip mode timing........................................................................90 7.1.6 transmit packet with vlan tag replace timing ..................................91 7.1.7 vlan tag append in two txsel_l bursts ...............................................92 7.1.8 vlan tag replace in two txsel_l bursts...............................................93 7.1.9 transmit fifo control timing................................................................93 7.1.10 transmit txrdy timing.............................................................................94 7.1.11 receive start-of-packet timing..............................................................94 7.1.12 receive end-of-packet timing...............................................................95 7.1.13 receive packet timing in split mode.....................................................96 7.1.14 receive rxfail timing ..............................................................................97 7.1.15 receive rxabt timing..............................................................................98 7.1.16 receive rxkep timing.............................................................................99 7.1.17 receive header replay timing............................................................100 7.1.18 receive fifo control timing...............................................................100 7.1.19 receive rxrdy control timing ...............................................................101 7.1.20 consecutive transmit-transmit timing................................................101 7.1.21 consecutive transmit-receive timing.................................................102 7.1.22 consecutive receive-transmit timing.................................................102 7.1.23 consecutive receive-receive timing..................................................103 7.2 gmii/gpcs port timing diagrams....................................................................103 7.2.1 packet transmission timing ................................................................103 7.2.2 packet reception timing .....................................................................104 7.2.3 false carrier timing.............................................................................104 intel ? ixf1002 dual port gigabit ethernet controller vi datasheet 8.0 electrical and environmental specifications .................................................................. 105 8.1 functional operating range ............................................................................. 105 8.2 absolute maximum rating ................................................................................ 105 8.3 supply current and power dissipation ............................................................. 106 8.4 temperature limit ratings................................................................................ 106 8.5 reset specification ........................................................................................... 106 8.6 fifo port specifications ................................................................................... 106 8.6.1 clock specification............................................................................... 106 8.6.2 3 volt dc specifications....................................................................... 107 8.6.3 5 volt dc specifications....................................................................... 108 8.6.4 ix bus signals timing .......................................................................... 108 8.7 cpu port specifications.................................................................................... 109 8.7.1 dc specifications ................................................................................. 109 8.7.2 signals timing...................................................................................... 109 8.7.2.1 read timing ............................................................................ 109 8.7.2.2 write timing ............................................................................ 110 8.7.2.3 timing parameters .................................................................. 110 8.8 gmii/gpcs port specifications ........................................................................ 111 8.8.1 dc specifications ................................................................................. 111 8.8.2 signals timing...................................................................................... 111 8.8.2.1 clocks specifications .............................................................. 111 8.8.2.2 gmii signals timing diagrams................................................ 112 8.8.2.3 gmii signals timing parameters ............................................ 113 8.8.2.4 gpcs signals timing diagrams ............................................. 113 8.8.2.5 gpcs signals timing parameters .......................................... 114 8.9 jtag port specifications .................................................................................. 114 8.9.1 dc specifications ................................................................................. 114 8.9.2 signals timing...................................................................................... 115 9.0 mechanical specifications.............................................................................................. 117 a joint test action group ? test logic ............................................................................. 121 a.1 general description .......................................................................................... 121 a.1.1 test access port controller.................................................................. 121 a.2 registers ........................................................................................................... 121 a.2.1 instruction register .............................................................................. 122 a.2.2 bypass register ................................................................................... 122 a.2.3 boundary-scan register ...................................................................... 122 b glossary ...................................................................................................................... ... 123 b.1 list of abbreviations.......................................................................................... 123 c multi-packet mode ......................................................................................................... 125 c.1 overview ........................................................................................................... 125 c.2 introduction - txrdy assertion/deassertion rules .............................................. 125 c.3 multi-packet mode ............................................................................................ 126 c.4 port working mode register ............................................................................. 126 datasheet vii intel ? ixf1002 dual port gigabit ethernet controller figures 1 block diagram ...................................................................................................... 9 2 full-64 ix bus mode............................................................................................60 3 narrow ix bus mode ...........................................................................................60 4 split ix bus mode................................................................................................60 5 little endian, full-64 bus mode (bend=0, fifmd=01)......................................61 6 little endian, split bus mode (bend=0, fifmd=10)..........................................61 7 little endian, narrow bus mode (bend=0, fifmd=00) .....................................61 8 big endian, full-64 bus mode (bend=1, fifmd=01) ........................................61 9 big endian, split bus mode (bend=0, fifmd=10) ............................................61 10 big endian, narrow bus mode (bend=1, fifmd=00)........................................61 11 vlan tagged mac frame format .....................................................................63 12 vlan tag append ..............................................................................................65 13 vlan tag strip ...................................................................................................65 14 vlan tag replace..............................................................................................66 15 transmit flow diagram .......................................................................................67 16 receive flow diagram ........................................................................................72 17 mac frame format.............................................................................................79 18 transmit start-of-packet timing..........................................................................87 19 transmit end-of-packet timing...........................................................................88 20 transmit packet timing in split mode.................................................................88 21 transmit packet with vlan tag append timing.................................................89 22 transmit packet with vlan tag strip timing......................................................90 23 transmit packet with vlan tag replace timing................................................91 24 vlan tag append in two txsel_l bursts timing.................................................92 25 vlan tag replace in two txsel_l bursts timing................................................93 26 transmit fifo control timing.............................................................................93 27 transmit txrdy timing..........................................................................................94 28 receive start-of-packet timing...........................................................................94 29 receive end-of-packet timing............................................................................95 30 receive packet timing in split mode..................................................................96 31 receive rxfail timing ...........................................................................................97 32 receive rxabt timing...........................................................................................98 33 receive rxkep timing..........................................................................................99 34 receive header replay timing.........................................................................100 35 receive fifo control timing............................................................................100 36 receive rxrdy timing.........................................................................................101 37 consecutive transmit-transmit timing.............................................................101 38 consecutive transmit-receive timing..............................................................102 39 consecutive receive-transmit timing..............................................................102 40 consecutive receive-receive timing...............................................................103 41 packet transmission timing .............................................................................103 42 packet reception timing ..................................................................................104 43 false carrier timing..........................................................................................104 44 ix bus clock timing diagram ...........................................................................106 45 ix bus signals timing diagram.........................................................................108 46 cpu port read timing diagram .......................................................................109 47 cpu port write timing diagram .......................................................................110 48 gmii clock timing diagram ..............................................................................111 49 gpcs transmit clock timing diagram.............................................................111 intel ? ixf1002 dual port gigabit ethernet controller viii datasheet 50 gpcs receive clock timing diagram.............................................................. 112 51 gmii port transmit timing diagram ................................................................. 112 52 gmii port receive timing diagram .................................................................. 112 53 gpcs port transmit timing diagram ............................................................... 113 54 gpcs receive timing diagram........................................................................ 113 55 jtag port timing diagram ............................................................................... 115 56 part marking...................................................................................................... 117 57 304-esbga package........................................................................................ 118 tables 1 component description....................................................................................... 10 2 signal descriptions ............................................................................................. 11 3 ixf1002 pin count.............................................................................................. 17 4 pin list ................................................................................................................ 18 5 csr register mapping ....................................................................................... 22 6 network statistic register mapping .................................................................... 55 7 ix bus receive packet status ............................................................................ 69 8 snmp mib to ixf1002 counters mapping ......................................................... 74 9 rmon statistics to ixf1002 counters mapping................................................. 74 10 rmon host to ixf1002 counters mapping........................................................ 75 11 gmii port signals versus standard signals ........................................................ 78 12 ethernet frame description ................................................................................ 79 13 flow-control field matching ............................................................................... 83 14 gpcs port signal description ............................................................................ 84 15 functional operating range ............................................................................. 105 16 absolute maximum rating ................................................................................ 105 17 supply current and power dissipation ............................................................. 106 18 temperature limit ratings................................................................................ 106 19 ix bus clock timing specifications................................................................... 107 20 ix bus 3.3 v signaling specifications ............................................................... 107 21 ix bus 5 v signaling specifications .................................................................. 108 22 ix bus signals timing specifications ................................................................ 108 23 cpu port dc specifications.............................................................................. 109 24 timing parameters............................................................................................ 110 25 gmii/gpcs port dc specifications .................................................................. 111 26 gmii/gpcs port signals timing specifications................................................ 112 27 signals timing parameters .............................................................................. 113 28 gpcs signals timing parameters.................................................................... 114 29 jtag port dc specifications............................................................................. 114 30 jtag port timing specifications ...................................................................... 115 31 304-esbga dimensional attributes.................................................................. 119 intel ? ixf1002 dual port gigabit ethernet controller datasheet 9 1.0 introduction 1.1 general description the intel ? ixf1002 dual-port gigabit ethernet controller includes two full-duplex independent 1000 mb/s ethernet controllers and interfaces directly to gigabit ethernet standard transceivers through its gigabit media independent interface (gmii) or gpcs interface. the ixf1002 handles simple network management protocol (snmp) and remote monitoring (rmon) management counter sets, accessible through a generic cpu 8/16-bit interface, which is also used for mode programming. each mac port includes a 4 kbyte fifo for packet receive, and a 2 kbyte fifo for packet transmit. all the packets are transferred onto a high-performance, common ix bus interface. the ixf1002 cpu and ix bus interfaces are compatible to the intel ? 21440 octal fast ethernet controller device. the ixf1002 is fully compatible with ieee 802.3x and 802.3z standards, including auto-negotiation and flow-control support. it is implemented in a low-power 3.3 v cmos device within a 304-esbga package. 1.2 block diagram figure 1 shows the ixf1002 block diagram. figure 1. block diagram a4965-02 control port 0 jtag cpu bus fifo bus (ix bus) gpcs/gmii gpcs/gmii mgmt counts receive fifo transmit fifo receive mac 8b10b receive gpcs 8b10b transmit gpcs transmit mac port 1 intel ? ixf1002 dual port gigabit ethernet controller 10 datasheet 1.3 hardware overview table 1 describes the ixf1002 components. table 1. component description component description transmit fifo a 2 kbyte buffer for temporary storage of transmitted packets. the transmit fifo has direct interface to the ix bus. receive fifo a 4 kbyte buffer for temporary storage of received packets. supports packet deletion in case of errors. the receive fifo has direct interface to the ix bus. transmit mac implements the ieee 802.3 transmit full-duplex mac functions while interfacing between the transmit fifo and the gmii phy or the gpcs function. receive mac implements the ieee 802.3 receive full-duplex mac functions while interfacing between the receive fifo and the gmii phy or the gpcs function. gpcs implementing the 1000base-x pcs layer that includes the auto-negotiation synchronization and encoding/decoding functions. snmp and rmon handles network statistic counters for snmp and rmon. control handles the chip registers accessible through the cpu bus. jtag includes the jtag technologies ieee 1149.1 (jtag) boundary scan logic. intel ? ixf1002 dual port gigabit ethernet controller datasheet 11 2.0 pinout this chapter describes the ixf1002 pinouts. 2.1 signal description table 2 describes the ixf1002 signals. the following conventions are used in the signal names: the following abbreviations are used in table 2 : _l: indicates that the pin is active low. {i}: the i subscript appended to pin names indicates that each port has its own pin (numbered from 0 to 1). intel ? ixf1002 dual port gigabit ethernet controller 12 datasheet cdat<15:0> i/o cpu data bus. in 8 bit mode (default): cdat<7:0> carries data to be written to or read from the registers. cdat<15:8> should be connected to pull up resistors. in 16 bit mode: cdat<15:0> carries data to be written to or read from the registers. cint{i}_l od interrupt lines. these signals are asserted following a variety of programmable conditions. deassertion occurs after reading the events that cause the interrupt, unless another interrupt is registered meanwhile. reset_l i general reset. upon reset, all the registers are reset to their default values and the fifos are flushed. reset_l assertion time should be at least 1 ms. ix bus interface clamp i vdd clamp. should be connected to the power of the highest signal level used on the ix bus. clk i system clock. all the fifo data transfers are synchronized to this clock. txsel_l i transmit select. this pin must be asserted to enable transmit fifo write access. rxsel_l i receive select. this pin must be asserted to enable receive fifo read access. the following signals are driven by the ixf1002 upon assertion of rxsel_l: fdat<63:0>, fbe_l<7:0>, sop, eop and rxfail in full-64 ix bus mode . fdat<31:0>, fbe_l<3:0>, sop_rxf, eop_rxf and rxfail in split ix bus mode . fdat<31:0>, fbe_l<3:0>, sop, eop and rxfail in narrow ix bus mode . fps/fps_rxf i fifo port select. in full-64 mode and in narrow mode (fps): when asserted, selects port no. 1 for data transfer through the ix bus. when deasserted, selects port no. 0 for data transfer through the ix bus. in split mode(fps_rxf): selects one of the ports for reading data, through fdat<31:0>, from the receive fifo of the selected port. fps_txf i fifo port select. in full-64 mode and in narrow mode: not in use, should be connected to pull up resistors. in split mode: selects one of the ports for writing data, through fdat<63:32>, to the transmit fifo of the selected port. table 2. signal descriptions (sheet 2 of 6) signal name i/o pin description intel ? ixf1002 dual port gigabit ethernet controller datasheet 13 fdat<63:0> i/o fifo data bus. in full-64 mode: fdat<63:0> (i/o) carries the data to be written to the transmit fifo or read from the receive fifo of the selected port. in split mode: fdat<31:0> (output) carries the data to be read from the receive fifo of the selected port. fdat<63:32> (input) carries the data to be written to the transmit fifo of the selected port. in narrow mode: fdat<31:0> (i/o) carries the data to be written to the transmit fifo or to be read from the receive fifo of the selected port. fdat<63:32> should be connected to pull up resistors. fbe_l<7:0> i/o fifo byte enable. in full-64 mode: during transmit, fbe_l<7:0> indicates which of the bytes driven onto fdat<63:0> contain valid data (valid bytes need to be contiguous and at least one byte must be valid). during receive, fbe_l<7:0> indicates which bytes are valid. each fbe_l signal relates to a different fdat byte (for example, fbe_l<0> relates to fdat<7:0> and fbe_l<5> relates to fdat<47:40>). in split mode: fbe_l<3:0> (output) relates to fdat<31:0> that is directed out of the port (receive fifo). fbe_l<7:4> (input) indicates valid data on fdat<63:32> that is directed into the port (transmit fifo). in narrow mode: fbe_l<3:0> (i/o) relates to fdat<31:0> that is directed in/out of the port. fbe_l<7:4> should be connected to pull up resistors. rxkep i receive keep. when asserted, this signal causes the last read data to be kept in the receive fifo. may be asserted only with rxsel_l assertion. sop/sop_rxf i/o start of packet. in full-64 mode and in narrow mode (sop ? i/o): when asserted during transmit, indicates that the first data in the packet is transferred to the transmit fifo. during receive, this signal is asserted when the first data in the packet is transferred from the receive fifo to the ix bus. in split mode (sop_rxf ? output): during receive, this signal is asserted when the first data in the packet is transferred from the receive fifo to the ix bus. sop_txf i start of packet. in full-64 mode and in narrow mode: this signal is not in use and should be connected to a pull up resistor. in split mode: during transmit, indicates that the first data in the packet is written to the transmit fifo. table 2. signal descriptions (sheet 3 of 6) signal name i/o pin description intel ? ixf1002 dual port gigabit ethernet controller 14 datasheet eop/eop_rxf i/o end of packet. in full-64 mode and in narrow mode (eop ? i/o): when asserted during transmit, indicates that the final data in the packet is written to the transmit fifo. during receive, eop is asserted when the final data of the packet is transferred from the receive fifo to the ix bus. in split mode (eop_rxf ? output): during receive, eop_rxf is asserted when the final data of the packet is transferred from the receive fifo to the ix bus. in the following fifo access cycle, the packet status is driven onto the bus (see section 4.3.1.1 ). eop_txf i end of packet. in full-64 mode and in narrow mode: this signal is not in use and should be connected to a pull up resistor. in split mode: during transmit, indicates that the final data in the packet is written to the transmit fifo. vtg i vlan tag. when asserted during transmit before sop assertion, vlan tag will be appended to the transmitted packet. when asserted during transmit together with sop assertion, vlan tag will be stripped from the transmitted packet. when asserted during transmit before and also together with sop assertion, vlan tag will be replaced. see section 4.2.2 for more details. note: in case of vlan tag append, strip or replace, the frame check sequence (fcs) field will be calculated by the ixf1002 (see section 4.2.2.1 ). txasis/txerr i transmit as is/transmit error. when asserted during transmit, upon transfer of the packet ? s first data (together with sop assertion), no padding and/or crc is appended to the packet even if the port was programmed to do so. when asserted upon transfer of the packet ? s final data (together with eop assertion), the packet is transmitted with a crc error (if the port is programmed to append crc), and a gmii error or a symbol error (gpcs mode). rxfail o receive packet failure. this signal is asserted if a packet was received with errors, had started to appear on the ix bus, and was discarded from the receive fifo. rxabt i receive abort. this signal forces a received packet, that is currently being transferred to the ix bus, to be aborted and flushed from the receive fifo. may be asserted only with rxsel_l assertion. any following packets loaded onto the receive fifo are not affected by rxabt assertion. flct_{i} i flow control. when asserted, a flow-control packet with the programmed pause time is transmitted. upon deassertion, a flow-control packet with time equal to 0 is sent if programmed accordingly. for correct latch of flct pin in the chip - signal flct_{i} should be valid until 1 cycle after flct_lat deassertion. flct_lat i flow control pin enable when asserted the flct_{i} pin will be sampled by the ixf1002. when deasserted, the ixf1002 will latch the value of the flct_{i} pin, ignoring subsequent changes to the flct_{i} pin. txctl_l i transmit control enable. when asserted, this pin enables the txrdy_{i} output drivers to report the transmit fifo status. rxctl_l i receive control enable. when asserted, this pin enables the rxrdy_{i} output drivers to report the receive fifo status. table 2. signal descriptions (sheet 4 of 6) signal name i/o pin description intel ? ixf1002 dual port gigabit ethernet controller datasheet 15 txrdy_{i} o transmit fifo ready. indicates whether there is enough available space in the transmit fifo to load data according to the programmable threshold value. following transmission stop due to an error, the txrdy signal remains deasserted until the transmit error status is read. rxrdy_{i} o receive fifo ready. indicates whether there is enough available data in the receive fifo to be stored according to the programmable threshold value or if the end of the transferred packet is in the fifo. the rxrdy signal may also be programmed to assert when the packet header is in the fifo. rxrdy can also be asserted to report packet discard from the receive fifo due to an error together with the rxfail signal. gmii / gpcs interface note: the following pins have various functions according to the port mode: gmii or gpcs. for a detailed description, turn to section 6.0 . tclk i 125 mhz clock for reference. gtxclk_{i}/pmatclk_{i} o gmii mode: 125 mhz transmit clock. gpcs mode: 125 mhz transmit clock. txd_{i}<7:0> o gmii mode: byte transmit data. gpcs mode: eight low bits of the encoded transmit data. ten{i}/txd{i}<8> o gmii mode: transmit enable signal. gpcs mode: the ninth bit of the encoded transmit data. terr{i}/txd{i}<9> o gmii mode: transmit error signal. gpcs mode: the tenth bit of the encoded transmit data. rclk_{i} i gmii mode: receive recovered 125 mhz clock. gpcs mode: the 62.5 mhz recovered receive byte clock. used to latch odd numbered bytes of the receive data. pmarclk_{i} i gmii mode: not in use, should be connected to a pull up resistor. gpcs mode: the 62.5 mhz recovered receive byte clock. used to latch even numbered bytes of the receive data. rxd_{i}<7:0> i gmii mode: byte receive data. gpcs mode: eight low bits of the encoded received data. dv{i}/rxd{i}<8> i gmii mode: receive enable signal. gpcs mode: the ninth bit of the encoded received data. rerr{i}/rxd{i}<9> i gmii mode: receive error signal. gpcs mode: the tenth bit of the encoded received data. sd_{i} i gmii mode: not in use, should be connected to a pull up resistor. gpcs mode: signal detect. indicates whether the phy has detected an input signal at the serial input. if this signal is not driven into the ixf1002, port_mode intel ? ixf1002 dual port gigabit ethernet controller 16 datasheet ewrap_{i} o gmii mode: not in use, should be connected to a pull up resistor. gpcs mode: enable wrap. when asserted, the phy should loop the transmit serialized data to the receive section. this pin is controlled by bit lpbk in the gmii management control register (gmii_ctl). lckref_l_{i} o gmii mode: not in use, should be connected to a pull up resistor. gpcs mode: lock to reference. when asserted, enables the phy to lock its pll to the 125 mhz reference clock. this pin is controlled by bit lcke in the port_mode register. encdet_{i} o gmii mode: not in use, should be left unconnected. gpcs mode: enable comma detect. when asserted, enables the phy for comma detect and word resynchronization. when deasserted, the phy will keep current word alignment and will not try to detect new commas. comdet_{i} i gmii mode: not in use, should be connected to a pull up resistor. gpcs mode: comma detect. an indication from the phy layer that the data contains a valid comma character. mdc i/o gmii management clock. this pin is output after reset. should be connected to a pull-up resistor. mdc can be used as a general purpose pin according to the gmii_mgng_acc register. the mdc pin drives 0 by default and its output enable is controlled by bit mdcen in register mii_mng_acc. mdio i/o gmii management input/output serial data. should be connected to a pull up resistor. mdio can be used as a general purpose pin according to the gmii_mgng_acc register. jtag interface tck i jtag clock. if this pin is not used, it must be connected to 0. tms i jtag test mode. if this pin is not used, it must be connected to 1. tdi i jtag data serial input. if this pin is not used, it must be connected to 1. tdo o jtag data serial output. table 2. signal descriptions (sheet 6 of 6) signal name i/o pin description intel ? ixf1002 dual port gigabit ethernet controller datasheet 17 2.2 pin count table 3 summarizes the ixf1002 pin count. 2.3 connection rules all the reserved pins must remain unconnected. all the open drain (od) signals must be connected to a pull-up device. all signals connected to a fixed value should be connected through a resistive device. the following are recommended resistor values: ? unused i/o pins: 10 k ? pull-up ? unused i pins: 1 ? 10 k ? pull-up or pull-down ? unused o pins: no pull-up required ? od pins: r=t/c (required signal deassertion time (t) divided by capacitive load (c)) note: unless otherwise specified, all defined pins that are not in use must be connected to a pull-up device. table 3. ixf1002 pin count block common per port total cpu 32 1 34 fifo 90 3 96 gmii/gpcs 3 30 63 jtag 4 4 total i/o 129 68 197 gnd 36 36 vdd 36 36 reserved 35 35 total 236 68 304 intel ? ixf1002 dual port gigabit ethernet controller 18 datasheet 2.4 pin list table 4 lists the ixf1002 pins. pins associated names are to be defined. table 4. pin list (sheet 1 of 3) pin number pin name pin number pin name pin number pin name aa11 act_0 h3 clamp c1 fdat<5> y23 act_1 c12 clk e4 fdat<6> n22 cadd<0> w2 comdet_0 d3 fdat<7> n21 cadd<1> ac13 comdet_1 d5 fdat<8> n20 cadd<2> t21 cps a3 fdat<9> p23 cadd<3> t20 crd_l b4 fdat<10> p22 cadd<4> v22 crdy_l c5 fdat<11> r23 cadd<5> u22 cs_l a4 fdat<12> p20 cadd<6> u21 cwr_l b5 fdat<13> r22 cadd<7> ab5 dv_0/rxd0<8> c6 fdat<14> r21 cadd<8> ab16 dv_1/rxd1<8> d7 fdat<15> t22 cadd<9> y7 encdet_0 b6 fdat<16> u2 cdat<0> aa17 encdet_1 c7 fdat<17> t3 cdat<1> h4 eop/eop_rxf d8 fdat<18> u1 cdat<2> g3 eop_txf b7 fdat<19> t2 cdat<3> ac5 ewrap_0 c8 fdat<20> r2 cdat<4> ab18 ewrap_1 a7 fdat<21> p4 cdat<5> l3 fbe_l<0> b8 fdat<22> r1 cdat<6> l4 fbe_l<1> b9 fdat<23> p3 cdat<7> k1 fbe_l<2> d10 fdat<24> p2 cdat<8> k2 fbe_l<3> a9 fdat<25> p1 cdat<9> j1 fbe_l<4> c10 fdat<26> n4 cdat<10> j2 fbe_l<5> b10 fdat<27> n3 cdat<11> j3 fbe_l<6> a10 fdat<28> n1 cdat<12> h2 fbe_l<7> c11 fdat<29> m2 cdat<13> f3 fdat<0> b11 fdat<30> m3 cdat<14> e2 fdat<1> a11 fdat<31> l1 cdat<15> d1 fdat<2> a13 fdat<32> u20 cint_1_l e3 fdat<3> c13 fdat<33> w23 cint_0_l d2 fdat<4> d13 fdat<34> intel ? ixf1002 dual port gigabit ethernet controller datasheet 19 a14 fdat<35> a6 gnd ab6 gtxclk_0 b14 fdat<36> a8 gnd y16 gtxclk_1 c14 fdat<37> a12 gnd ab11 lckref_l_0 a15 fdat<38> a16 gnd w22 lckref_l_1 d14 fdat<39> a18 gnd y11 lnk_0 c15 fdat<40> a22 gnd w21 lnk_1 b16 fdat<41> aa22 gnd ac11 mdc c16 fdat<42> b1 gnd aa12 mdio a17 fdat<43> b3 gnd a21 nc d16 fdat<44> b21 gnd b13 nc c17 fdat<45> b23 gnd b15 nc b18 fdat<46> c2 gnd b17 nc a19 fdat<47> c22 gnd c20 nc d17 fdat<48> f1 gnd c4 nc c18 fdat<49> f23 gnd c9 nc b19 fdat<50> h1 gnd d11 nc a20 fdat<51> h23 gnd d19 nc c19 fdat<52> m1 gnd e21 nc b20 fdat<53> m23 gnd g2 nc d21 fdat<54> t1 gnd g21 nc e20 fdat<55> t23 gnd g4 nc c23 fdat<56> v1 gnd j23 nc d22 fdat<57> v23 gnd k23 nc d23 fdat<58> aa2 gnd k3 nc e22 fdat<59> ab1 gnd k4 nc f21 fdat<60> ab3 gnd l2 nc g20 fdat<61> ab21 gnd n2 nc e23 fdat<62> ab23 gnd n23 nc f22 fdat<63> ac2 gnd p21 nc l23 flct_0 ac6 gnd r3 nc m22 flct_1 ac8 gnd t4 nc l22 flct_lat ac12 gnd u23 nc g22 fps/fps_rxf ac16 gnd v3 nc h20 fps_txf ac18 gnd y13 nc a2 gnd ac22 gnd y14 nc table 4. pin list (sheet 2 of 3) pin number pin name pin number pin name pin number pin name intel ? ixf1002 dual port gigabit ethernet controller 20 datasheet y19 nc g23 rxfail a1 vcc aa4 nc l20 rxrdy_0 a23 vcc aa9 nc l21 rxrdy_1 b2 vcc aa20 nc ab10 sd_0 b22 vcc ac4 nc y22 sd_1 c3 vcc ac10 nc e1 sop/sop_rxf c21 vcc ac21 nc f2 sop_txf d4 vcc v21 nc u3 tck d6 vcc aa5 pmarclk_0 u4 tdo d9 vcc aa16 pmarclk_1 w1 tdi d12 vcc ab4 rclk_0 y8 ten0/txd0<8> d15 vcc ac17 rclk_1 y17 ten1/txd1<8> d18 vcc ab12 tclk aa7 terr0/txd0<9> d20 vcc aa6 rerr0/rxd0<9> ac19 terr1/txd1<9> f4 vcc ab17 rerr1/rxd1<9> v2 tms f20 vcc m21 reset_l h21 txasis/txerr j4 vcc h22 rxkep j22 txctl_l j20 vcc a5 rxsel_l aa10 txd_0<0> m4 vcc j21 rxabt ac9 txd_0<1> m20 vcc k20 rxctl_l y10 txd_0<2> r4 vcc y1 rxd_0<0> ab9 txd_0<3> r20 vcc w3 rxd_0<1> ab8 txd_0<4> v4 vcc y2 rxd_0<2> aa8 txd_0<5> v20 vcc aa1 rxd_0<3> ac7 txd_0<6> y4 vcc w4 rxd_0<4> ab7 txd_0<7> y6 vcc y3 rxd_0<5> aa23 txd_1<0> y9 vcc y5 rxd_0<6> w20 txd_1<1> y12 vcc ac3 rxd_0<7> y21 txd_1<2> y15 vcc ab13 rxd_1<0> ab20 txd_1<3> y18 vcc aa13 rxd_1<1> aa19 txd_1<4> y20 vcc ac14 rxd_1<2> ac20 txd_1<5> aa3 vcc ab14 rxd_1<3> ab19 txd_1<6> aa21 vcc aa14 rxd_1<4> aa18 txd_1<7> ab2 vcc ac15 rxd_1<5> k21 txrdy_0 ab22 vcc ab15 rxd_1<6> k22 txrdy_1 ac1 vcc aa15 rxd_1<7> b12 txsel_l ac23 vcc g1 vtg table 4. pin list (sheet 3 of 3) pin number pin name pin number pin name pin number pin name intel ? ixf1002 dual port gigabit ethernet controller datasheet 21 3.0 registers description this section describes the ixf1002 registers. each of the ixf1002 ports includes an independent register set, enabling maximum flexibility. the registers in each port are divided into two groups: control and status registers (csrs) network statistics counters 3.1 register conventions all the registers in the ixf1002 are implemented in each of its two ports, unless mentioned otherwise in the text. in the register description tables throughout this section, the following abbreviations are used to indicate register access modes: 3.1.1 access rules the following access rules must be followed when accessing registers: unlisted addresses are reserved and must not be accessed. the resolution of the addresses is in bytes. in 8-bit mode, access to the eight high or low bits of a register will be done directly to the address of the desired byte. in 16-bit mode, registers must be accessed with even addresses. reserved bits on registers must be written as 0 and are unpredictable on read. all registers, except port_ctl, are writable only when the port is in stop state (as reported in the interrupt status register ? int_stt), following transmit and receive disable programming. multibyte registers are ordered from low to high (the lower address points to the lower byte). r = readable only. w = writable only. r/w = readable and writable. intel ? ixf1002 dual port gigabit ethernet controller 22 datasheet 3.2 csr register this describes the ixf1002 csr register mapping. 3.2.1 register mapping table 5 lists each csr register name, mnemonic, address, and the section that describes the register. table 5. csr register mapping register description mnemonic i/o address 1 1. the offset to the strongarm ? core is 0x38408000. this address is required to access the csrs from the core. section base registers 3.2.2 interrupt status register int_stt 00h ? 01h 3.2.2.1 interrupt enable register int_en 02h ? 03h 3.2.2.2 port control register port_ctr 04h ? 05h 3.2.2.3 identification and revision number register id_rev 06h ? 07h 3.2.2.4 transmit and receive status register tx_rx_stt 08h ? 09h 3.2.2.5 transmit counter overflow status register tx_ov_stt 0ah ? 0dh 3.2.2.6 receive counter overflow status register rx_ov_stt 0eh ? 11h 3.2.2.7 configuration registers 3.2.3 transmit and receive error mode register tx_rx_err 20h ? 21h 3.2.3.1 fifo threshold register ffo_tshd 22h ? 23h 3.2.3.2 port working mode register port_mode 24h ? 25h 3.2.3.3 transmit and receive parameter register tx_rx_param 26h ? 27h 3.2.3.4 transmit threshold register tx_tshd 28h ? 29h 3.2.3.5 transmit flow-control pause time register pause_time 2ah ? 2bh 3.2.3.6 maximum packet size register pkt_max_size 2ch ? 2dh 3.2.3.7 inter packet gap value ipg_val 2eh ? 2fh 3.2.3.8 mac address register mac_add 30h ? 35h 3.2.3.9 vlan tag length/type register vlan_tag 36h ? 37h 3.2.3.10 transmit counter overflow mask register tx_ov_msk 38h ? 3bh 3.2.3.11 receive counter overflow mask register rx_ov_msk 3ch ? 3fh 3.2.3.12 gmii management access registers (used in gmii mode) 3.2.4 gmii management access register gmii_mng_acc 4ah ? 4bh 3.2.4.1 gmii management data register gmii_mng_dat 4ch ? 4dh 3.2.4.2 gmii management register set (used in gpcs mode) 3.2.5 gmii control register gmii_ctl 50h ? 51h 3.2.5.1 gmii status register gmii_stt 52h ? 53h 3.2.5.2 an advertisement register an_adv 58h ? 59h 3.2.5.3 an link partner ability base page register an_prt_abl 5ah ? 5bh 3.2.5.4 an expansion register an_exp 5ch ? 5dh 3.2.5.5 an next page transmit register an_np_tr 5eh ? 5fh 3.2.5.6 an link partner receive next page register an_prt_np 60h ? 61h 3.2.5.7 extended status register gmii_ext_stt 6eh ? 6fh 3.2.5.8 gpcs status register gpcs_stt 70h ? 71h 3.2.5.9 intel ? ixf1002 dual port gigabit ethernet controller datasheet 23 3.2.2 base registers the following sections describe the individual base registers. 3.2.2.1 interrupt status register mnemonic: int_stt address: 00h ? 01h the interrupt status register handles information regarding events that cause an interrupt. a specific event sets a bit if it was programmed to generate an interrupt in the interrupt enable register (int_en). reading this register will reset all the bits, except for pkev and ovfc bits. these bits are reset only when the asserted bits in the relevant status registers are reset by read. bit name bit # bit description ? 15 reserved stop 14 port stop. indicates that transmit or receive path is in the stop state, following disable programming in the port control register. if both transmit and receive paths are programmed to be stopped, this bit is set when they both reach the stop state. ovfc 13 counter overflow. indicates that at least one network statistic counter has reached its highest possible value. this bit is a logical or of all bits in the counter overflow status registers (see section 3.2.2.6 and section 3.2.2.7 ). lnch 12 link change. indicates that a link change has occurred while working in gpcs mode. the actual link status is reported in the gmii status register gmii_stt intel ? ixf1002 dual port gigabit ethernet controller 24 datasheet 3.2.2.2 interrupt enable register mnemonic: int_en address: 02h ? 03h each bit in this register, when set to 1, enables the generation of an interrupt when the corresponding event occurs. the event causing the interrupt will be reported in the interrupt status register (int_stt). 3.2.2.3 port control register mnemonic: port_ctr address: 04h ? 05h access rules register access r value after reset 0000h bit name bit # bit description bit name bit # bit description ? 15 reserved stope 14 port stop interrupt enable. ovfce 13 counter overflow interrupt enable. lnche 12 link change interrupt enable. ? 11 reserved txoke 10 transmit ok interrupt enable. pkeve 9 packet event interrupt enable. rxoke 8 receive ok interrupt enable. anere 7 auto-negotiation error interrupt enable. pgrce 6 page received interrupt enable. ? 5:0 reserved access rules register access r/w value after reset 0000h a4967-01 1514131211109876543210 s t o p e o v f c e l n c h e t x o k e p k e v e r x o k e a n e r e p g r c e intel ? ixf1002 dual port gigabit ethernet controller datasheet 25 the port control register handles all the control bits of the port. bit name bit # bit description ? 15:9 reserved fct 8 flow-control packet trigger. when set, initiates a flow-control packet transmission to the remote node, as defined in the 802.3x ieee standard. the pause time field in the transmitted packet will be copied from the pause_time register (see section 3.2.3.6 ). ? 7:6 reserved txstt 5 transmit restart. when set, the chip restarts the transmission process after stopping due to a transmit error. the txstt is a trigger bit (does not require reset before setting). txen 4 transmit enable. when this bit is set, the port enters the transmit working mode. when reset, the port completes transmission of the packet currently processed, and then stops. stop state is reported in the stop bit located in the interrupt status register (int_stt). rxen 3 receive enable. when this bit is set, the port enters the receive working mode. when reset, the port completes reception of the packet currently processed, and then stops. stop state is reported in the stop bit located in the interrupt status register (int_stt). ptrst 2 port reset. when set, this bit causes the transmit and receive logic to reset. setting this bit will not reset the control registers. ctrst 1 control reset. when set, this bit resets all the registers, except port_ctr, to their default values. transmit and receive logic are also reset. this bit is not self clearing, it requires set and then reset. cnrst 0 counter reset. when set, this bit resets all the network statistic counters. the cnrst is a trigger bit (does not require resetting before setting.) access rules register access r/w bit 5 and bit 8 are trigger bits and are write only. value after reset 0000h a4968-01 1514131211109876543210 f c t t x e n t x s t t r x e n p t r s t c t r s t c n r s t intel ? ixf1002 dual port gigabit ethernet controller 26 datasheet 3.2.2.4 identification and revision register mnemonic: id_rev address: 06h ? 07h the identification and revision register is valid only in port 0. 3.2.2.5 transmit and receive status register mnemonic: tx_rx_stt address: 08h ? 09h this register reports events that have occurred during packet reception and transmission. all bits, except pkc bit, are reset upon reading this register. the unf bit is set only if packet transmission is programmed to be stopped following fifo underflow in the transmit and receive error mode register (tx_rx_err intel ? ixf1002 dual port gigabit ethernet controller datasheet 27 3.2.2.6 transmit counter overflow status register mnemonic: tx_ov_stt address: 0ah ? 0dh the transmit counter overflow status register reports overflow events of each transmit counter. when a counter reaches its highest possible value, it will continue to count from zero, and the corresponding status bit will be set. reading this register will reset all the bits, and will clear the interrupt if it was activated. bit name bit # bit description flc 15 flow-control packet. indicates that a flow-control packet was received. ? 14 reserved mer 13 gmii error. indicates either that a symbol error was detected in the gpcs mode or that an gmii error signal was asserted in the gmii mode during packet reception. rtl 12 too long packet. indicates that a packet longer than the maximum allowable packet size specified in the pkt_max_size register, has been received. srt 11 short packet. indicates that a packet shorter than 64 bytes has been received. ? 10 reserved crc 9 crc error. indicates that a packet was received with a crc error. ovf 8 fifo overflow. indicates that there was not enough space available in the receive fifo during packet reception. pkc 7:6 packet count. indicates the number of packets currently stored in the transmit fifo. the packet count is incremented while loading the first byte of a packet and decremented following transmission of a packet. the maximum number of packets that can be in the transmit fifo is two. ? 5:1 reserved unf 0 fifo underflow. indicates that data was not available in the transmit fifo during packet transmission. access rules register access r value after reset 0000h a4971-01 151413121110987654321 30 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 t x _ u n i t x _ m l t t x _ b r d t x _ 6 4 t x _ 6 5 t x _ 1 2 8 t x _ 2 5 6 t x _ 5 1 2 t x _ 1 0 2 4 t x _ 1 5 1 9 t x _ p s t x _ e r t x _ o k t x _ b d intel ? ixf1002 dual port gigabit ethernet controller 28 datasheet 3.2.2.7 receive counter overflow status register mnemonic: rx_ov_stt address: 0eh ? 11h the receive counter overflow status register reports overflow events of each receive counter. when a counter reaches its highest possible value, it will continue to count from zero, and the corresponding status bit will be set. reading this register will reset all the bits, and will clear the interrupt if it was activated. bit name bit # bit description ? 31:20 reserved tx_bd 19 tx_oct_bad_cnt counter overflow. tx_ok 18 tx_oct_ok_cnt counter overflow. tx_er 17 tx_err_cnt counter overflow. tx_ps 16 tx_pause_cnt counter overflow. tx_1519 15 tx_pkt_1519_cnt counter overflow. tx_1024 14 tx_pkt_1024_cnt counter overflow. tx_512 13 tx_pkt_512_cnt counter overflow. tx_256 12 tx_pkt_256_cnt counter overflow. tx_128 11 tx_pkt_128_cnt counter overflow. tx_65 10 tx_pkt_65_cnt counter overflow. tx_64 9 tx_pkt_64_cnt counter overflow. ? 8:3 reserved tx_brd 2 tx_brd_ok_cnt counter overflow. tx_mlt 1 tx_mlt_ok_cnt counter overflow. tx_uni 0 tx_uni_ok_cnt counter overflow. access rules register access r value after reset 0000h a4972-02 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 30 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r x _ o k r x _ b d r x _ n _ c r r x _ b r d r x _ m l t r x _ u n i r x _ s _ c r r x _ s _ o k r x _ o v r x _ l _ o k r x _ l c r r x _ 6 4 r x _ 6 5 r x _ 1 2 8 r x _ 2 5 6 r x _ 5 1 2 r x _ 1 0 2 4 r x _ 1 5 1 9 r x _ e r r x _ f a l r x _ p s intel ? ixf1002 dual port gigabit ethernet controller datasheet 29 bit name bit # bit description ? 31:23 reserved rx_er 22 rx_gpcs_err_cnt counter overflow. rx_fal 21 rx_fals_crs_cnt counter overflow. rx_ps 20 rx_pause_cnt counter overflow. rx_1519 19 rx_pkt_1519_cnt counter overflow. rx_1024 18 rx_pkt_1024_cnt counter overflow. rx_512 17 rx_pkt_512_cnt counter overflow. rx_256 16 rx_pkt_256_cnt counter overflow. rx_128 15 rx_pkt_128_cnt counter overflow. rx_65 14 rx_pkt_65_cnt counter overflow. rx_64 13 rx_pkt_64_cnt counter overflow. rx_l_cr 12 rx_long_crc_cnt counter overflow. ? 11 reserved rx_l_ok 10 rx_long_ok_cnt counter overflow. rx_n_cr 9 rx_norm_crc_cnt counter overflow. rx_brd 8 rx_brd_ok_cnt counter overflow. rx_mlt 7 rx_mlt_ok_cn counter overflow. rx_uni 6 rx_uni_ok_cnt counter overflow. rx_s_cr 5 rx_short_crc_cnt counter overflow. rx_s_ok 4 rx_short_ok_cnt counter overflow. rx_ov 3 rx_ovf_cnt counter overflow. ? 2 reserved rx_bd 1 rx_oct_bad_cnt counter overflow. rx_ok 0 rx_oct_ok_cnt counter overflow. access rules register access r value after reset 0000h intel ? ixf1002 dual port gigabit ethernet controller 30 datasheet 3.2.3 configuration registers the following sections describe the individual configuration registers. 3.2.3.1 transmit and receive error mode register mnemonic: tx_rx_err address: 20h ? 21h this register defines the actions to be performed following a transmit or receive error. when a receive packet with a specific event is programmed to be passed, the corresponding packets are not discarded and are transferred as regular packets. the transmit and receive events are reported in the transmit and receive status register (tx_rx_stt) and can generate an interrupt according to the interrupt enable register (int_en). if a specific event is not programmed to enable reception of a packet, the corresponding packets are discarded from the receive fifo. failure will be reported onto the rxfail signal if the packet has already started to be transferred onto the ix bus. if a packet with multiple errors is to be passed, all corresponding bits must be set. bit name bit # bit description pflc 15 pass flow-control packets. ? 14 reserved pmer 13 pass packets with gmii error. prtl 12 pass too long packets. psrt 11 pass short packets. ? 10 reserved pcrc 9 pass crc error packets. povf 8 pass fifo overflow. ? 7:1 reserved unfs 0 stop transmission after fifo underflow. when set, the transmit fifo is flushed and transmission stops if an underflow occurs. when transmission is stopped after fifo underflow, flow-control packets can still be transmitted. a value of 1 in this bit will be followed by activation of pkev interrupt if it is enabled (see section 3.2.2.1 ), and not by the port stop interrupt. when reset, if an underflow occurs the packet will be flushed from the transmit fifo, and the following packet will be transmitted. access rules register access r/w value after reset 0000h a4973-01 1514131211109876543210 p f l c p m e r p r t l p s r t p c r c p o v f u n f s intel ? ixf1002 dual port gigabit ethernet controller datasheet 31 3.2.3.2 fifo threshold register mnemonic: ffo_tshd address: 22h ? 23h the fifo register handles the transmit and receive fifo threshold. bit name bit # bit description ? 15:14 reserved tth 13:8 this field defines the minimum amount of free space required in the transmit fifo in order to assert the txrdy signal. the effective threshold in bytes is equal to 16 (tth + 1). ? 7 reserved rth 6:0 this field defines the minimum amount of data required in the receive fifo in order to assert the rxrdy signal. the effective threshold in bytes is equal to 16 (rth + 1). access rules register access r/w value after reset 0303h a4974-01 1514131211109876543210 t t h r t h intel ? ixf1002 dual port gigabit ethernet controller 32 datasheet 3.2.3.3 port working mode register mnemonic: port_mode address: 24h ? 25h the port mode register controls the cpu bus, ix bus, and serial interface modes of work. note: details on multi-packet mode (available with the gcixf1002ed) are contained in appendix c.4 . note: bits 12, 11, 2, and 0 must have the same value in both ports. bit name bit # bit description ? 15:13 reserved fifmd 12:11 ix bus mode: this field sets the ix bus mode. both ports of the ixf1002 must be operating in the same ix bus mode. the table below shows the ix bus mode according to bits 12 and 11. bit 12 bit 11 mode 0 0 narrow-32 bit mode 0 1 full-64 bit mode 1 0 split mode 1 1 reserved in the full-64 bit mode, the 64 bits fdat<63:0> are used for either transmitting or receiving data. in the split mode, the 32 lower bits fdat<31:0> are used for receiving packets from the receive fifo and the 32 higher bits fdat<63:32> are used for transmitting packets to the transmit fifo. in the narrow mode, the lower 32 bits fdat<31:1> are used for either transmitting or receiving packets. hryd 10 header ready disable. when set, the rxrdy signal will not be asserted when a packet header is in fifo, but only according to fifo threshold values. ps_d 9 packet status disable. when set, the packet status will not be appended to received packets that are transferred onto the ix bus. when reset, the packet status is appended to any packet completely transferred onto the ix bus, and is driven onto the ix bus in the access following the last byte transfer ( see 4.3.1.1 ). bend 8 big or little endian mode. defines the byte ordering mode on the ix bus. when set, the port uses the big endian mode. when reset, the little endian mode is used. a4975-01 1514131211109876543210 h r y d p s ? d b e n d l c k e f x e c d i l p k f i f m d g p c s s d d i s c p u b w intel ? ixf1002 dual port gigabit ethernet controller datasheet 33 lcke 7 enable activation of lock to reference signal. when set, the lckref_{i} signal will be asserted to the phy when there is no activity (no signal detected) on the line. used only in gpcs mode. fxecd 6 fix enable comma detect signal. when set, the encdet_{i} signal to the phy will be continuously asserted. when cleared, the encdet_{i} signal will be asserted only during loss of synchronization. used only in gpcs mode. ilpk 5 internal loopback mode. when set, the port is disconnected from the line and all the transmitted packets are sent back to the receive side. packets are not transmitted onto the line and packets received from the line are rejected. ? 4:3 reserved cpubw 2 cpu data bus width. when asserted, bus width is 16, all cdat<15:0> bits are in use. when deasserted, bus width is 8, indicating that the 8 low bits cdat<7:0> are in use. sddis 1 signal detect disable. setting this bit will cause ixf1002 to consider the value of the sd{i} input signal as high, regardless to the actual value on the pin. used only in gpcs mode. gpcs 0 gpcs port mode. this bit defines the gmii/gpcs port mode. if a gpcs phy device is connected, this bit must be set. if a gmii phy device is connected, this bit must be reset. access rules register access r/w value after reset 0000h bit name bit # bit description intel ? ixf1002 dual port gigabit ethernet controller 34 datasheet 3.2.3.4 transmit and receive parameters register mnemonic: tx_rx_param address: 26h ? 27h the transmit and receive parameters register handles the control of the serial interface. bit name bit # bit description crcr 15 crc remove. when set, the last four bytes of the received packet will not be transferred onto the ix bus. packets shorter than 4 bytes will be discarded. hrpl 14 header replay. when set, packet header is transferred twice onto the ix bus. hdrs 13:8 header size. header size is used for the header replay function and for rxrdy signal assertion (even if the header replay function is disabled). the header size is calculated in bytes as 4 hdrs (hdrs > 4). ? 7:6 reserved adfc 5 additional flow control. when this bit is asserted, the ixf1002 will send an additional flow-control packet if a flow-control packet was sent upon assertion of the flct_{i} signal, and while this signal was asserted, the link partner ? s pause time period was about to end. this will cause the link partner to receive the additional flow-control packet before its pause time counting ends. note: this feature is operative only if xond bit is equal to 0. spm 4 single packet mode. when set, a packet is loaded in the transmit fifo only after the previous packet was transmitted onto the serial line. when not set, the transmit fifo can contain a maximum of two packets. xond 3 xon disable. when set, a flow-control packet with pause time equal to zero, will not be sent upon flct_{i} signal deassertion. rflce 2 receive flow-control mode enable. when set, transmission is paused upon receiving flow-control packets. note: this bit is used only in gmii mode and in gpcs mode when auto-negotiation is disabled (gmii_ctl intel ? ixf1002 dual port gigabit ethernet controller datasheet 35 3.2.3.5 transmit threshold register mnemonic: tx_tshd address: 28h ? 29h the transmission threshold register handles the packet transmission threshold. 3.2.3.6 transmit flow-control pause time register mnemonic: pause_time address: 2ah ? 2bh the transmit flow-control pause time register handles the time field used in the transmitted flow-control packets. access rules register access r/w value after reset 1004h bit name bit # bit description bit name bit # bit description ? 15:8 reserved tsd 7:0 packet transmission threshold. packet transmission starts when the amount of data in the transmit fifo is larger than or equal to the threshold, or the entire packet enters onto the fifo. the effective threshold in bytes is equal to 8 tsd + 4. if the sum of the effective serial threshold and the effective parallel threshold bring the system to a deadlock, the transmission can start before threshold is reached to prevent deadlock. (tsd > 1) access rules register access r/w value after reset 0003h a4977-01 1514131211109876543210 tsd a4978-01 1514131211109876543210 ptsm intel ? ixf1002 dual port gigabit ethernet controller 36 datasheet bit name bit # bit description pstm 15:0 indicates the number of units of 512 bit time (512 ns), during which the remote node cannot send packets. this field is inserted into the transmitted flow-control packets. access rules register access r/w value after reset 0000h intel ? ixf1002 dual port gigabit ethernet controller datasheet 37 3.2.3.7 maximum packet size register mnemonic: pkt_max_size address: 2ch ? 2dh this register controls the maximum allowed received packet size. 3.2.3.8 inter packet gap value register mnemonic: ipg_val address: 2eh ? 2fh this register controls the inter packet gap value between transmitted packets. bit name bit # bit description mps 15:0 packets received with a longer size are treated as too long packets. access rules register access r/w value after reset 05eeh (1518 decimal) a4979-01 1514131211109876543210 mps bit name bit # bit description ? 15:5 reserved ipg 4:0 interpacket gap value in units of 8 bit time. this field must get a minimum value of 6h (48-bit time). access rules register access r/w value after reset 000ch (96-bit time) a4980-01 1514131211109876543210 ipg intel ? ixf1002 dual port gigabit ethernet controller 38 datasheet 3.2.3.9 mac address registers mnemonic: mac_add address: 30h ? 35h the mac address register contains the ethernet physical address of the port. this address is inserted into transmitted flow-control packets in the source address field. 3.2.3.10 vlan tag length/type register mnemonic: vlan_tag address: 36h ? 37h the vlan length/type register is used to define the vlan tag length/type field. bit name bit # bit description ead 47:0 port ethernet address. bit 47 is the most significant bit, and bit 0 is the least significant bit and is the first bit of the mac serial bit stream. access rules register access r/w value after reset 0000h a4981-01 47 40 32 24 16 8 0 . . . . . . . . . . . . . . . . . . ead bit name bit # bit description vlan_t yp 15:0 vlan type this field defines length/type field of the vlan tag when inserted into transmitted frames. a4982-01 1514131211109876543210 vlan_typ intel ? ixf1002 dual port gigabit ethernet controller datasheet 39 3.2.3.11 transmit counter overflow mask register mnemonic: tx_ov_msk address: 38h ? 3bh the transmit counter overflow mask register enables masking of specific transmit counters overflow interrupt. masking a counter does not influence the setting of the counter overflow status bit in tx_ov_stt. access rules register access r/w value after reset 8100h bit name bit # bit description bit name bit # bit description ? 31:20 reserved tx_bd 19 mask tx_oct_bad_cnt counter overflow. tx_ok 18 mask tx_oct_ok_cnt counter overflow. tx_er 17 mask tx_err_cnt counter overflow. tx_ps 16 mask tx_pause_cnt counter overflow. tx_1519 15 mask tx_pkt_1519_cnt counter overflow. tx_1024 14 mask tx_pkt_1024_cnt counter overflow. tx_512 13 mask tx_pkt_512_cnt counter overflow. tx_256 12 mask tx_pkt_256_cnt counter overflow. tx_128 11 mask tx_pkt_128_cnt counter overflow. tx_65 10 mask tx_pkt_65_cnt counter overflow. tx_64 9 mask tx_pkt_64_cnt counter overflow. ? 8:3 reserved tx_brd 2 mask tx_brd_ok_cnt counter overflow. tx_mlt 1 mask tx_mlt_ok_cnt counter overflow. tx_uni 0 mask tx_uni_ok_cnt counter overflow. a4983-01 151413121110987654321 30 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 t x _ u n i t x _ m l t t x _ 6 5 t x _ 6 4 t x _ b r d t x _ 1 2 8 t x _ 2 5 6 t x _ 5 1 2 t x _ 1 0 2 4 t x _ 1 5 1 9 t x _ p s t x _ e r t x _ o k t x _ b d intel ? ixf1002 dual port gigabit ethernet controller 40 datasheet access rules register access r/w value after reset 0000h bit name bit # bit description intel ? ixf1002 dual port gigabit ethernet controller datasheet 41 3.2.3.12 receive counter overflow mask register mnemonic: rx_ov_msk address: 3ch ? 3fh the receive counter overflow mask register enables masking of specific receive counters overflow interrupt. masking a counter does not influence the setting of the counter overflow status bit in rx_ov_stt bit name bit # bit description ? 31:23 reserved rx_er 22 mask rx_gpcs_err_cnt counter overflow. rx_fal 21 mask rx_fals_crs_cnt counter overflow. rx_ps 20 mask rx_pause_cnt counter overflow. rx_1519 19 mask rx_pkt_1519_cnt counter overflow. rx_1024 18 mask rx_pkt_1024_cnt counter overflow. rx_512 17 mask rx_pkt_512_cnt counter overflow. rx_256 16 mask rx_pkt_256_cnt counter overflow. rx_128 15 mask rx_pkt_128_cnt counter overflow. rx_65 14 mask rx_pkt_65_cnt counter overflow. rx_64 13 mask rx_pkt_64_cnt counter overflow. rx_l_cr 12 mask rx_long_crc_cnt counter overflow. ? 11 reserved rx_l_ok 10 mask rx_long_ok_cnt counter overflow. rx_n_cr 9 mask rx_norm_crc_cnt counter overflow. rx_brd 8 mask rx_brd_ok_cnt counter overflow. rx_mlt 7 mask rx_mlt_ok_cn counter overflow. rx_uni 6 mask rx_uni_ok_cnt counter overflow. rx_s_cr 5 mask rx_short_crc_cnt counter overflow. rx_s_ok 4 mask rx_short_ok_cnt counter overflow. rx_ov 3 mask rx_ovf_cnt counter overflow. ? 2 reserved rx_bd 1 mask rx_oct_bad_cnt counter overflow. rx_ok 0 mask rx_oct_ok_cnt counter overflow. a4984-01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 30 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r x ? l ? c r r x ? l ? o k r x ? n ? c r r x ? s ? o k r x ? s ? c r r x ? b r d r x ? m l t r x ? u n i r x ? e r r x ? f a l r x ? p s r x ? 1 5 1 9 r x ? 1 0 2 4 r x ? 5 1 2 r x ? 2 5 6 r x ? 1 2 8 r x ? 6 5 r x ? 6 4 r x ? o v r x ? b d r x ? o k intel ? ixf1002 dual port gigabit ethernet controller 42 datasheet 3.2.4 gmii management access registers this set of registers is intended to simplify access to the gmii management registers in the phy, while working in gmii mode. in order to access a gmii management register in the phy, an access command should be written in the gmii management access register (gmii_mng_acc). the ixf1002 carries out the command and accesses the phy through the mdc and mdio pins. in gpcs mode, the set of gmii management registers is provided on the ixf1002 in addresses 50h ? 71gh, and these addresses should be accessed directly. note: these registers are valid only in port 0. 3.2.4.1 gmii management access register mnemonic: gmii_mng_acc address: 4ah ? 4bh (only in port 0) the gmii management access register controls the mdc and mdio i/o pins. two modes of access to the phy are available direct access mode: in this mode each of the mdc and mdio i/o pins are set to be input or output, and can be read or written through this register. automatic access mode: this mode is used to access the gmii management register set in the phy. the address of the desired phy and register, and the mode of access (r/w), are defined in this register. in this mode the ixf1002 will transmit and receive frames to/from the phy through the mdc and mdio pins, as defined in the 802.3u standard. the automatic access will begin after writing a value of 1 to the amam bit, if the cpu is in the 16-bit mode, or after a write access to the high byte of this register if the value of the amam bit is 1 and the cpu is in 8-bit mode. use bits mdc/mdio as gpio by writing to register gmii_mng_acc. they are used in the direct access mode as follows: ama (bit 0) = 0 mdio (bit 15) is used to drive the mdio pin (or read from it) mdc (bit 14) is used to drive the mdio pin mdcen (bit 13) enables the mdc pin as an output rwgmi (bit 12) enables the mdio pin as an output you can write to the register and drive these pins, and read the pin ? s value by reading the register (with enable bits reset). access rules register access r/w value after reset 0000h bit name bit # bit description intel ? ixf1002 dual port gigabit ethernet controller datasheet 43 bit name bit # bit description mdio 15 gmii data io in direct access mode (amam=0): during mdio write access (rwgmi=1), the value written to this bit is driven onto the mdio signal. during mdio read access (rwgmi=0), the mdio signal value is latched into this bit. in automatic access mode (amam=1): this bit is not valid. mdc 14 mdc clock value in direct access mode (amam=0): during mdc write access (mdcen=1), the value written to this bit is driven onto the mdc signal. when access to the phy is done using this bit, each new value must remain stable for at least 200 ns. during mdc read access (mdcen=0), the mdc signal value is latched into this bit. in automatic access mode (amam=1): this bit is not valid mdcen 13 enable mdc output in direct access mode (amam=0): when set enables mdc output. in automatic access mode (amam=1): this bit is not valid. rwgmi 12 read/write gmii management registers. in direct access mode (amam=0): when set enables mdio output. in automatic access mode (amam=1): set this bit for writing the data from the gmii_mng_dat register into the gmii management desired register. reset this bit for reading the gmii management desired register into the gmii_mng_dat register. phy_add 11:7 gmii phy address. the address of the desired phy. bit 11 is the most significant bit and is the first phy address bit to be transmitted and received. reg_add 6:2 gmii register address. the address of the desired register. bit 6 is the most significant bit and is the first register address bit to be transmitted and received. a4985-02 1514131211109876543210 r w g m i m d c e n m d c m d i o phy_add reg_add g m i r y a m a m intel ? ixf1002 dual port gigabit ethernet controller 44 datasheet 3.2.4.2 gmii management data register mnemonic: gmii_mng_dat address: 4ch ? 4dh (only in port 0) in read mode, this register will get the value of the desired gmii management register. in write mode, the desired management register will get the value of this register. note: when cpu bus is in 8 bit mode, write access to this register must be done to both addresses, starting at the low address. gmiry 1 gmii management access registers are ready. this bit indicates whether the access to the gmii management registers had been completed. during the access process, the value of this bit will be 0. the bit will be set at the end of the process. writing to the gmii management access registers while this bit is cleared will be ignored, although the crdy_l signal will be asserted. amam 0 automatic mdio access mode setting this bit will begin the automatic access. note: if the cpu bus is in 8-bit mode the automatic access will occur after a write access to the high byte of the register. access rules register access during gmii automatic access (gmiry = 0) r, otherwise r/w. value after reset 0003h bit name bit # bit description bit name bit # bit description gmii_dt 15:0 gmii data. bit 15 is the most significant bit, corresponding to bit 15 of the accessed register. bit 0 is the least significant bit. access rules register access bits 12:2 , during gmii automatic access (gmii_mng_acc intel ? ixf1002 dual port gigabit ethernet controller datasheet 45 3.2.5 gmii management register set the following sections describe the individual gmii management register set as defined in the ieee 802.3z standard. any bit in these registers that has a fixed value is not writable. note: these registers are accessible only in gpcs mode. 3.2.5.1 gmii control register mnemonic: gmii_ctl address: 50h ? 51h the control register provides the mechanism to enable or disable auto-negotiation, restart auto-negotiation, and allow for manual configuration when auto-negotiation is disabled. bit name bit # bit description rst 15 reset. when set, causes reset to the gpcs logic and to the gmii management registers. when reset, indicates normal operation. this bit is self clearing. the value of this bit remains at 1, until the reset process is completed. lpbk 14 external loopback. when set, enables external loopback mode, and causes assertion of ewrap_{i} signal. when reset, disables external loopback mode, and causes deassertion of ewrap_{i} signal. speed_2 13 speed selection. this bit is fixed at the value of 0 and the value of bit 6 is fixed to 1, determining a speed selection of 1000 mb/s. anenbl 12 auto-negotiation enable. when set, auto-negotiation process is enabled. when reset, auto-negotiation process is disabled. pwrd 11 power down. this bit is fixed at the value of 0. the ixf1002 gpcs does not support the power down function. islt 10 isolate. this bit is fixed at the value of 0. the ixf1002 gpcs does not support the isolate function. a4987-01 1514131211109876543210 a n e n b l s p e e d _ 2 l p b k r s t s p e e d _ 1 c o l l t s t d u p l e x r e s a n i s l t p w r d intel ? ixf1002 dual port gigabit ethernet controller 46 datasheet 3.2.5.2 gmii status register mnemonic: gmii_stt address: 52h ? 53h the gmii status register includes information about all modes of operations supported by the local device and the status of auto-negotiation. resan 9 restart auto-negotiation. when set, restarts auto-negotiation process. when reset, indicates normal operation. this bit is self clearing. the value of this bit will change back to 0 when the auto-negotiation process is initiated. if auto-negotiation is disabled (anenbl=0), this bit should be at a value of 0. duplex 8 duplex mode. this bit is fixed at the value of 1. the ixf1002 is operating only in the full-duplex mode. colltst 7 collision test. this bit is fixed at the value of 0. the ixf1002 gpcs does not support the collision signal test. speed_1 6 speed selection. this bit is fixed at the value of 1 and the value of bit 13 is fixed at 0, determining a speed selection of 1000 mb/s ? 5:0 reserved. access rules register access bits 9, 12, 14, 15 r/w, bits 6, 7, 8, 10, 11, 13 r. value after reset 1140h bit name bit # bit description bit name bit # bit description 100t4 15 100base-t4 ability. this bit is fixed at the value of 0. 100xfd 14 100base-x full-duplex ability. this bit is fixed at the value of 0. 100xhd 13 100base-x half-duplex ability. this bit is fixed at the value of 0. a4988-01 1514131211109876543210 1 0 f d 1 0 0 x h d 1 0 0 x f d 1 0 0 t 4 m f p r e a n c m p l r m t f l t a n a b l t j b r d t c e x t c a p l n k s t t e x t s t t 1 0 0 t 2 h d 1 0 0 t 2 f d 1 0 h d intel ? ixf1002 dual port gigabit ethernet controller datasheet 47 10fd 12 10 mb/s full-duplex ability. this bit is fixed at the value of 0. 10hd 11 10 mb/s half-duplex ability. this bit is fixed at the value of 0. 100t2fd 10 100base-t2 full-duplex ability. this bit is fixed at the value of 0. 100t2hd 9 100base-t2 half-duplex ability. this bit is fixed at the value of 0. extstt 8 extended status. this bit is fixed at the value of 1, indicating additional status information in the extended status register (gmii_ext_stt). ? 7 reserved mfpre 6 mf preamble suppression. this bit is fixed at the value of 0. the ixf1002 registers cannot be accessed through the mdio pin. ancmpl 5 auto-negotiation complete. a value of 1 indicates that auto-negotiation process is completed. a value of 0 indicates that auto-negotiation process is not completed. rmtflt 4 remote fault. a value of 1 indicates that a remote fault condition was detected in the link partner ? s base page. a value of 0 indicates that a remote fault condition was not detected. anablt 3 auto-negotiation ability. this bit is fixed at the value of 1, indicating that the gpcs is able to perform auto-negotiation. lnkstt 2 link status. a value of 1 indicates that the link is up. a value of 0 indicates that the link is down. link up is defined as a status in which the synchronization process and the auto-negotiation process were completed and the device is ready to transmit or receive data. jbrdtc 1 jabber detect. this bit is fixed at the value of 0. the ixf1002 gpcs does not support jabber detection. extcap 0 extended capability. this bit is fixed at the value of 0, indicating basic register set capabilities only. access rules register access r value after reset 0108h bit name bit # bit description intel ? ixf1002 dual port gigabit ethernet controller 48 datasheet 3.2.5.3 an advertisement register mnemonic: an_adv address: 58h ? 59h the an advertisement register contains the advertised ability of the local device. if another value than the default value is written into this register, then auto-negotiation should be restarted by setting bit gmii_ctl intel ? ixf1002 dual port gigabit ethernet controller datasheet 49 3.2.5.4 an link partner ability base page register mnemonic: an_prt_abl address: 5ah ? 5bh the an link partner ability base page register contains the advertised ability of the partner ? s device. this register is updated once every auto-negotiation process, at the end of the page exchange state. bit name bit # bit description nxtpg 15 next page. when set, indicates a request for next page exchange was made by the link partner. ack 14 acknowledge . when set, indicates that the link partner has successfully received the base page of the local device. rf 13:12 remote fault. the remote fault bits are used to notify the local device about a fault that had occurred at the link partner device. the table below specifies the remote fault encoding. <12> <13> description 0 0 no error, link ok 0 1 off line 1 0 link failure 1 1 auto-negotiation error 11:9 reserved asm_dir 8 asymmetric pause connection is desired. when set, results in independent enabling of the flow-control receive and transmit. when reset, results in symmetric enabling of the flow-control receive and transmit. pause 7 capable of configuring the pause function. when set, indicates that the link partner ? s device is capable and intends to stop upon reception of flow-control packets, as defined in ieee 802.3x. hd 6 half duplex. when set, indicates link partner ? s half-duplex capability. fd 5 full duplex. when set, indicates link partner ? s full-duplex capability. ? 4:0 reserved access rules register access r value after reset 0000h a4990-01 1514131211109876543210 r f n x t p g a c k f d h d p a u s e a s m _ d i r intel ? ixf1002 dual port gigabit ethernet controller 50 datasheet 3.2.5.5 an expansion register mnemonic: an_exp address: 5ch ? 5dh the an expansion register includes information about page reception and ability of next page function. bit name bit # bit description 15:8 reserved nprcv 7 next page received. a value of 1 in this bit, indicates that the link partner ? s current received page is a next page. a value of 0 in this bit indicates that the link partner ? s current received page is the base page. 6:3 reserved npabl 2 next page able. this bit is fixed at the value of 1. the ixf1002 has next page ability. pgrcv 1 page received. a value of 1 in this bit indicates that the link partner ? s base or next page has been received. bit #7 in this register indicates whether the received page is a base or next page. this bit is reset by read. 0 reserved access rules register access r value after reset 0004h a4991-01 1514131211109876543210 n p r c v p g r c v n p a b l intel ? ixf1002 dual port gigabit ethernet controller datasheet 51 3.2.5.6 an next page register mnemonic: an_np_tr address: 5eh ? 5fh the an next page transmit register contains the data that will be transmitted during next page exchange. note: when cpu bus is in 8 bit mode, write access to this register must be done to both addresses, starting at the low address. bit name bit # bit description nxtpg 15 next page. when set, indicates a request for an additional next page exchange was made by the link partner. ? 14 reserved mp 13 message page. this bit indicates whether this page is a message page or an unformatted page. ack2 12 acknowledge 2. this bit is used to indicate whether the device has the ability to comply with the message. ? 11 reserved encod 10:0 next page encoding. access rules register access bits 15, 13:0 r/w. bit 11 r. value after reset 0000h a4995-02 1514131211109876543210 n x t p g encod m p a c k 2 intel ? ixf1002 dual port gigabit ethernet controller 52 datasheet 3.2.5.7 an link partner receive next page register mnemonic: an_prt_np address: 60h ? 61h the an link partner receive next page register contains the data of the link parameter next page. bit name bit # bit description nxtpg 15 next page. when set, indicates a request for an additional next page exchange was made by the link partner. ? 14 reserved mp 13 message page. this bit indicates whether this page is a message page or an unformatted page. ack2 12 acknowledge 2. this bit is used to indicate whether the link partner ? s device has the ability to comply with the message. tgl 11 toggle . this bit should get the opposite value of the toggle bit in the previously exchanged page. encod 10:0 next page encoding. access rules register access r value after reset 0000h a4995-01 1514131211109876543210 n x t p g t g l encod m p a c k 2 intel ? ixf1002 dual port gigabit ethernet controller datasheet 53 3.2.5.8 extended status register mnemonic: gmii_ext_stt address: 6eh ? 6fh the extended status register includes information about giga bit modes of operations supported by the local device. bit name bit # bit description 1000xfd 15 1000base-x full-duplex ability. this bit is fixed at the value of 1. 1000xhd 14 1000base-x half-duplex ability. this bit is fixed at the value of 0. 1000tfd 13 1000base-t full-duplex ability. this bit is fixed at the value of 0. 1000thd 12 1000base-t half-duplex ability. this bit is fixed at the value of 0. 11:0 reserved access rules register access r value after reset 8000h a4996-01 1514131211109876543210 1 0 0 0 x f d 1 0 0 0 x h d 1 0 0 0 t f d 1 0 0 0 t h d intel ? ixf1002 dual port gigabit ethernet controller 54 datasheet 3.2.5.9 gpcs status register mnemonic: gpcs_stt address: 70h ? 71h the gpcs status register reports the parameters of the auto-negotiation and synchronization process. this register is used only in gpcs mode. bit name bit # bit description ? 15:6 reserved synst 5 synchronization status. a value of ? 0 ? indicates out of synchronization status. a value of ? 1 ? indicates that synchronization was acquired. ? 4:2 reserved lpps 1 link partner flow-control status. a value of ? 0 ? indicates that link partner ? s transmission will not be stopped upon reception of flow-control packets. a value of ? 1 ? indicates that link partner ? s transmission will be stopped upon reception of flow-control packets. rfc 0 receive flow-control status. a value of ? 0 ? indicates that transmission will not be stopped upon reception of flow-control packets. a value of ? 1 ? indicates that transmission will be stopped upon reception of flow-control packets. access rules register access r value after reset 0000h a4997-01 1514131211109876543210 s y n s t r f c l p p s intel ? ixf1002 dual port gigabit ethernet controller datasheet 55 3.3 network statistic counter mapping this section describes the ixf1002 statistic counter mapping. 3.3.1 register mapping table 6 lists each network statistic ixf1002 register name, mnemonic, and offset. i/o base address: 100h or 200h. table 6. network statistic register mapping (sheet 1 of 2) register description mnemonic i/o address offset transmit statistic counters the number of unicast packets transmitted without any errors. tx_uni_ok_cnt 00h ? 03h the number of multicast packets that are not broadcast, transmitted without any errors. tx_mlt_ok_cnt 04h ? 07h the number of broadcast packets transmitted without any errors. tx_brd_ok_cnt 08h ? 0bh the number of transmitted packets, 64 bytes in length, including bad packets. tx_pkt_64_cnt 24h ? 27h the number of transmitted packets, 65 to 127 bytes in length, including bad packets. tx_pkt_65_cnt 28h ? 2bh the number of transmitted packets, 128 to 255 bytes in length, including bad packets. tx_pkt_128_cnt 2ch ? 2fh the number of transmitted packets, 256 to 511 bytes in length, including bad packets. tx_pkt_256_cnt 30h ? 33h the number of transmitted packets, 512 to 1023 bytes in length, including bad packets. tx_pkt_512_cnt 34h ? 37h the number of transmitted packets, 1024 to 1518 bytes in length, including bad packets. tx_pkt_1024_cnt 38h ? 3bh the number of transmitted packets larger than 1518 bytes, including bad packets. tx_pkt_1519_cnt 3ch ? 3fh the number of correct transmitted flow-control packets. tx_pause_cnt 40h ? 43h the number of packets transmitted with an error due to transmit fifo underflow or txerr signal assertion. tx_err_cnt 44h ? 47h transmit byte counters the number of bytes transmitted in good packets. tx_oct_ok_cnt 60h ? 65h the number of bytes transmitted in packets with errors. tx_oct_bad_cnt 68h ? 6dh receive byte counters the number of bytes received in good packets. rx_oct_ok_cnt 70h ? 75h the number of bytes received in packets with errors. rx_oct_bad_cnt 78h ? 7dh receive statistic counters the number of receive packets not fully accepted due to receive fifo overflow. rx_ovf_cnt 84h ? 87h intel ? ixf1002 dual port gigabit ethernet controller 56 datasheet the number of packets, less than 64 bytes in length, received without any error. rx_short_ok_cnt 88h ? 8bh the number of packets less than 64 bytes in length, received with crc error. rx_short_crc_cnt 8ch ? 8fh the number of unicast packets with lengths between 64 bytes and the maximum packet size, received without any errors. rx_uni_ok_cnt 90h ? 93h the number of multicast packets with lengths between 64 bytes and the maximum packet size, received without any errors. rx_mlt_ok_cn 94h ? 97h the number of broadcast packets with lengths between 64 bytes and the maximum packet size, received without any errors. rx_brd_ok_cnt 98h ? 9bh the number of packets with lengths between 64 bytes and the maximum packet size, received with an integral number of bytes and a crc error. rx_norm_crc_cnt 9ch ? 9fh the number of packets, larger than the maximum packet size, received without any error. rx_long_ok_cnt a4h ? a7h the number of packets, larger than the maximum packet size, received with a crc error. rx_long_crc_cnt a8h ? abh the number of received packets, 64 bytes in length, including bad packets. rx_pkt_64_cnt ach ? afh the number of received packets, 65 to 127 bytes in length, including bad packets. rx_pkt_65_cnt b0h ? b3h the number of received packets, 128 to 255 bytes in length, including bad packets. rx_pkt_128_cnt b4h ? b7h the number of received packets, 256 to 511 bytes in length, including bad packets. rx_pkt_256_cnt b8h ? bbh the number of received packets, 512 to 1023 bytes in length, including bad packets. rx_pkt_512_cnt bch ? bfh the number of received packets, 1024 to 1518 bytes in length, including bad packets. rx_pkt_1024_cnt c0h ? c3h the number of received packets, with lengths between 1519 bytes and the maximum packet size (programmable value), including bad packets. rx_pkt_1519_cnt c4h ? c7h the number of correct received flow-control packets. rx_pause_cnt c8h ? cbh the number of false carrier events detected. rx_fals_crs_cnt cch ? cfh the number of received packets during which phy symbol errors were detected. rx_gpcs_err_cnt d0h ? d3h table 6. network statistic register mapping (sheet 2 of 2) register description mnemonic i/o address offset intel ? ixf1002 dual port gigabit ethernet controller datasheet 57 3.3.2 network statistic counters access rules the network statistic counters access rules are as follows: the counters can be accessed with a base address equal to 100h or 200h. accessing the counters with the 100h base address causes them to reset. accessing them with the 200h will not reset the counter. when the cpu data bus is in 16 bit mode, access to network statistic counters should be done only with even numbered addresses. the counters must be read from the lower to the upper bytes, in consecutive accesses. the statistic counters are not writable. note: when a counter reaches its highest possible value, it will continue to count from zero, and the corresponding counter overflow status bit will be set. note: receive statistic counters are updated even if the receive fifo overflows. note: all the byte counters take crc bytes into account, but exclude the framing bits in the packets. 3.4 access sequences this section describes the initialization, mode change, and interrupt handling sequences for the ixf1002. 3.4.1 initialization sequence each ixf1002 port must be initialized according to the following sequence: 1. disable the port and reset it by writing a value of 07h to the port control register (port_ctr) and then writing 00h to clear the reset. 2. initialize the port by writing to the relevant configuration registers. 3. enable port operation by writing a value of 18h to the port control register (port_ctr). 3.4.2 mode change sequence in order to change the ixf1002 working mode without impacting packet transfer, the following sequence must be used: 1. disable the port by writing a value of 00h to the port control register (port_ctr). 2. wait until the port enters the stop state. the stop state entry may generate an interrupt if enabled, and is reported by the stop bit in the interrupt status register (int_stt intel ? ixf1002 dual port gigabit ethernet controller 58 datasheet 3.4.3 interrupt handling sequence following interrupt, the subsequent sequence must be used to reset the interrupt: 1. if both ports are sharing the same interrupt line, perform steps 2 to 4 for each port that generates an interrupt. 2. read the port interrupt status register (int_stt) and act according to the interrupt cause. 3. if the packet event bit is set (int_stt intel ? ixf1002 dual port gigabit ethernet controller datasheet 59 4.0 ix bus interface operation this section describes the ixf1002 ix bus interface operation, including the transmission and reception flows. 4.1 ix bus interface the ixf1002 uses a generic bus interface for data transfer to and from its fifos. the data bus is 64 bits wide and has three modes of operation. big and little endian byte ordering are both supported on 32-bit boundaries (port_mode intel ? ixf1002 dual port gigabit ethernet controller 60 datasheet 4.1.2 byte ordering on ix bus on the ix bus, bytes are ordered according to the endian mode (port_mode intel ? ixf1002 dual port gigabit ethernet controller datasheet 61 figure 5. little endian, full-64 bus mode (bend=0, fifmd=01) figure 6. little endian, split bus mode (bend=0, fifmd=10) figure 7. little endian, narrow bus mode (bend=0, fifmd=00) figure 8. big endian, full-64 bus mode (bend=1, fifmd=01) figure 9. big endian, split bus mode (bend=0, fifmd=10) figure 10. big endian, narrow bus mode (bend=1, fifmd=00) a5452-01 8th byte 63 32 31 0 7th byte 6th byte 5th byte 4th byte 3rd byte 2nd byte 1st byte a5453-01 4th byte 63 transmit receive 32 31 0 3rd byte 2nd byte 1st byte 4th byte 3rd byte 2nd byte 1st byte a5454-01 31 0 4th byte 3rd byte 2nd byte 1st byte a5455-01 5th byte 63 32 31 0 6th byte 7th byte 8th byte 1st byte 2nd byte 3rd byte 4th byte a5456-01 1st byte 63 transmit receive 32 31 0 2nd byte 3rd byte 4th byte 1st byte 2nd byte 3rd byte 4th byte a5457-01 31 0 1st byte 2nd byte 3rd byte 4th byte intel ? ixf1002 dual port gigabit ethernet controller 62 datasheet 4.1.3 fifo status signaling the ixf1002 reports the status of each fifo through dedicated signals. each transmit fifo has a txrdy signal indicating that there is enough free space to load new data. each receive fifo has a rxrdy signal indicating that there is enough data to be transferred onto the ix bus. the txrdy signals are driven by the ixf1002 only when the txctl_l signal is asserted. the rxrdy signals are enabled by the rxclt_l signal.the txrdy signal of a specific port is deasserted when the txsel_l signal is asserted and the specific port is selected (fps). the same applies for the rxrdy signal of a specific port, which is deasserted with rxsel_l assertion and the specific port selection (fps). 4.2 packet transmission the following sections describe the packet transmission policy. note: the signal naming below refers to the full-64 ix bus mode. signal names should be changed in accordance to the bus mode as described in section 4.1.1.1 and section 4.1.1.2 . 4.2.1 packet loading the ixf1002 loads packets from the ix bus into the transmit fifo during burst accesses. in order to guarantee a minimal amount of data transfer, the transmit fifo txrdy signal reports minimal space availability according to a programmable threshold (ffo_tshd intel ? ixf1002 dual port gigabit ethernet controller datasheet 63 buffer 1: buffer 2: buffer 3: 4.2.2 vlan tagging the ixf1002 supports ieee p802.1q virtual bridged local area networks (vlan) standard. figure 11 shows the format of a tagged mac frame. this format is an extension of the basic mac frame, as specified in ieee 802.3 standard (see section 6.3 ). note: numbers in parentheses indicate field length in bytes. the qtag prefix field is 4 octets long. the first two octets transferred on to the network are called the tagged mac frame length/type field and contain a constant value of 8100h. the following two octets are called the tag control information field and are subdivided as follows: a three-bit user priority field a one-bit canonical format indicator (cfi) a 12-bit vlan identifier. a5458-01 b3 b11 b10 b9 b8 b7 b6 b5 b4 b2 b1 x x x x x x x x b12 xxxx a5459-01 x x x b14 b13 x x x a5460-01 x x x b21 b20 x x x x b19 b18 b17 b16 b15 x x figure 11. vlan tagged mac frame format a5461-01 preamble (7) (1) (6) (6) (4) (2) (46..1500) (4) qtag prefix destination address source address length/ type data+ padding length/ type control information sfd fcs intel ? ixf1002 dual port gigabit ethernet controller 64 datasheet note: the minimal frame length supported by vlan mode is 18 bytes. if the txasis signal is asserted together with the sop signal or tx_rx_param intel ? ixf1002 dual port gigabit ethernet controller datasheet 65 4.2.2.3 vlan tag strip for stripping a vlan tag from a vlan tagged mac frame, the following procedure should be performed: packet transmission for every vlan tagged mac frame transferred onto the ix bus, assert the vtg signal for one cycle at the beginning of the mac frame together with the assertion of the sop signal (see section 7.1.5 ). figure 13 shows the vlan tag strip. figure 12. vlan tag append a5462-02 ixf1002 fifo bus vlan tag vlan tagged mac frame basic mac frame figure 13. vlan tag strip a5463-02 ixf1002 fifo bus vlan tagged mac frame basic mac frame intel ? ixf1002 dual port gigabit ethernet controller 66 datasheet 4.2.2.4 vlan tag replace for replacing a vlan tag that exists in a vlan tagged mac frame with a new vlan tag, execute the vlan tag append and the vlan tag strip procedures on the same mac frame (see section 7.1.6 ). figure 14 shows vlan tag replacement 4.2.3 network transmission the ixf1002 will start to transmit the packet if there is enough data on the transmit fifo according to the programmable transmission threshold (tx_tshd intel ? ixf1002 dual port gigabit ethernet controller datasheet 67 4.2.4.1 stopping mode on transmission underflow error if the ixf1002 is programmed to stop after an underflow (tx_rx_err intel ? ixf1002 dual port gigabit ethernet controller 68 datasheet 4.3 packet reception the following sections describe the packet reception policy. note: the signal naming below refers to the full-64 ix bus mode. signal names should be changed in accordance to the bus mode as described in section 4.1.1.1 and section 4.1.1.2 . 4.3.1 packet storing packets received from the network are loaded into the receive fifo. received packets are transferred from the receive fifo onto the ix bus during burst accesses. to indicate the minimal amount of data available in the receive fifo, the rxrdy signal is asserted according to a programmable threshold. (ffo_tshd intel ? ixf1002 dual port gigabit ethernet controller datasheet 69 4.3.1.1 packet status when packet status mode is enabled (port_mode intel ? ixf1002 dual port gigabit ethernet controller 70 datasheet the packet header may also be read from the receive fifo for processing without removing it from the fifo. if the ixf1002 is programmed to work in the header replay mode (tx_rx_param intel ? ixf1002 dual port gigabit ethernet controller datasheet 71 4.3.4 packet abortion during the transfer of a received packet onto the ix bus, the ixf1002 supports the ability to prevent any further transfer of this packet. at any time during packet reception, the packet may be dynamically discarded from the receive fifo by asserting the rxabt signal during packet reading while rxsel_l signal is asserted. any subsequent packet loaded onto the receive fifo is not affected by rxabt assertion. the next fifo access will access the new packet. 4.3.5 network reception a packet received from the network is loaded to the receive fifo. if the packet is received without any error, it is transferred to the ix bus. if an error occurs during reception, the packet is handled according to the programming in the tx_rx_err register. the ixf1002 may be programmed to work in two modes: reject the erroneous packet or accept it. in both modes, the appropriate statistic counters will be updated (even if the packet was rejected due to packet error or fifo overflow), and any following packets will continue to be accepted and loaded to the receive fifo. the following events are considered as reception errors: fifo overflow crc error short packet too long packet gmii error 4.3.6 rejecting mode on reception errors if a packet with a reception error is programmed to be rejected (zero in the relevant bit of the tx_rx_err register). the ixf1002 discards the packet from the receive fifo without affecting previous packets that may still be in the receive fifo. if the packet had not yet started to be transferred on the ix bus, it will be discarded without affecting ix bus activity. if the packet had already started to be transferred onto the ix bus, or rxrdy was already asserted, the rxfail signal will be asserted on the next fifo access, indicating that the currently transferred packet was discarded from the receive fifo. packet status will not be driven for such a packet. 4.3.7 accepting mode on reception errors if a packet with a reception error is programmed to be accepted, (a 1 in the relevant bit of the tx_rx_err register), it is transferred to the ix bus as a regular packet. the event type is reported in the packet status appended to the end of the packet, and in the transmit and receive status register (tx_rx_stt). intel ? ixf1002 dual port gigabit ethernet controller 72 datasheet 4.3.8 receive flow diagram figure 16 shows the receive flow diagram. figure 16. receive flow diagram a5468-01 reset wait for new packet start receive flush packet from fifo assert rxfail signal on next fifo access report error in the receive status register and in the packet status good packet? pass on error? packet starts to appear on fifo bus? yes yes no no receive ok receive error intel ? ixf1002 dual port gigabit ethernet controller datasheet 73 5.0 cpu interface operation the following sections describe the cpu interface operation. 5.1 cpu interface the ixf1002 has a dedicated port for a cpu interface, enabling access to the different registers without interfering packet transfer through the fifos. the cpu interface is generic and supports a wide range of standard controllers. each of the two ixf1002 ports has its own independent registers. each of the port registers is accessible through an 8/16-bit-wide data bus and a 10-bit-wide address bus. a specific port is addressed by using the port select signal (cps), which may be considered a part of the address bus. each port has a dedicated interrupt signal (cint_l_{i}) to report special events to the cpu. the ixf1002 supports two cpu data bus widths: 8 (default) and 16 bit (controlled by the port_mode intel ? ixf1002 dual port gigabit ethernet controller 74 datasheet 5.2.1 snmp mib support the ixf1002 supports ethernet mib according to table 8 . 5.2.2 rmon statistic group support table 9 describes the ixf1002 support of the rmon statistic group. if packets are loaded into the ixf1002 to be transmitted as bad packets, they must be counted in the error counters, too. table 8. snmp mib to ixf1002 counters mapping snmp mac counters ixf1002 statistic counters framestransmittedok tx_uni_ok_cnt + tx_mlt_ok_cnt + tx_brd_ok_cnt framesreceivedok rx_uni_ok_cnt + rx_mlt_ok_cnt + rx_brd_ok_cnt frameschecksequenceerrors rx_norm_crc_cnt octetstransmittedok tx_oct_ok_cnt octetsreceivedok rx_oct_ok_cnt frametoolongerrors rx_long_ok_cnt + rx_long_crc_cnt multicastframesxmittedok x_mlt_ok_cnt broadcastframesreceivedok rx_brd_ok_cnt multicastframesreceivedok rx_mlt_ok_cnt broadcastframesxmittedok tx_brd_ok_cnt pauseframestransmitted tx_pause_cnt pauseframesreceived rx_pause_cnt table 9. rmon statistics to ixf1002 counters mapping (sheet 1 of 2) rmon statistic counters ixf1002 statistic counters etherstatsdropevents rx_ovf_cnt etherstatsoctets tx_oct_ok_cnt + tx_oct_bad_cnt + rx_oct_ok_cnt + rx_oct_bad_cnt etherstatspkts tx_uni_ok_cnt + rx_uni_ok_cnt + ether-statsbroadcastpkts + etherstatsmulticastpkts + etherstatscrcalignerrors + etherstatsundersizep-kts + etherstatsfragments + etherstatsoversizepkts + etherstatsjabber etherstatsbroadcastpkts tx_brd_ok_cnt + rx_brd_ok_cnt etherstatsmulticastpkts tx_mlt_ok_cnt + rx_mlt_ok_cnt etherstatscrcalignerrors rx_norm_crc_cnt + tx_err_cnt etherstatsundersizepkts rx_short_ok_cnt etherstatsoversizepkts rx_long_ok_cnt etherstatsfragments rx_short_crc_cnt etherstatsjabber rx_long_crc_cnt etherstatspkts64octets tx_pkt_64_cnt + rx_pkt_64_cnt etherstatspkts65to127octets tx_pkt_65_cnt + rx_pkt_65_cnt etherstatspkts128to255octets tx_pkt_128_cnt + rx_pkt_128_cnt intel ? ixf1002 dual port gigabit ethernet controller datasheet 75 5.2.3 rmon host group support table 10 describes the ixf1002 support of the rmon host group when a single node is connected to a port. if packets are loaded into the ixf1002 to be transmitted as bad packets, they must be counted in the error counters too. etherstatspkts256to511octets tx_pkt_256_cnt + rx_pkt_256_cnt etherstatspkts512to1023octets tx_pkt_512_cnt + rx_pkt_512_cnt etherstatspkts1024to1518octets tx_pkt_1024_cnt + rx_pkt_1024_cnt etherstatsdropevents rx_ovf_cnt etherstatsoctets tx_oct_ok_cnt + tx_oct_bad_cnt + rx_oct_ok_cnt + rx_oct_bad_cnt table 9. rmon statistics to ixf1002 counters mapping (sheet 2 of 2) rmon statistic counters ixf1002 statistic counters table 10. rmon host to ixf1002 counters mapping rmon host counters ixf1002 statistics counters hostinpkts tx_uni_ok_cnt + tx_mlt_ok_cnt + tx_brd_ok_cnt hostoutpkts rx_uni_ok_cnt + rx_mlt_ok_cnt + rx_brd_ok_cnt + rx_norm_crc_cnt + rx_short_ok_cnt + rx_short_crc_cnt + rx_long_ok_cnt + rx_long_crc_cnt hostinoctets tx_oct_ok_cnt hostoutoctets rx_oct_ok_cnt + rx_oct_bad_cnt hostouterrors rx_norm_crc_cnt + rx_short_ok_cnt + rx_short_crc_cnt + rx_long_ok_cnt + rx_long_crc_cnt hostoutbroadcastpkts rx_brd_ok_cnt hostoutmulticastpkts rx_mlt_ok_cnt intel ? ixf1002 dual port gigabit ethernet controller datasheet 77 6.0 network interface operation this section describes the gmii/gpcs port operation. it also describes media access control (mac), full-duplex, and loopback operations. the ixf1002 supports implementation of the mac sublayer according to the ieee 802.3z standard, in full-duplex mode. 6.1 operating modes each of the ixf1002 two ports supports gmii or gpcs interfaces. in the gmii mode, the gmii port provides a standard and simple interconnection between the mac sublayer and the phy layer. in this mode, the ixf1002 can be used with any device with an gmii interface that implements the 1000base-sx, 1000base-lx, 1000base-cx, or 1000base-t standards. the gmii interface comprises the following characteristics: supports 1000 mb/s data rate includes data and delimiters that are synchronous to clock references provides independent, 8-bit-wide transmit and receive data paths utilizes ttl signal levels provides a simple management interface through mdc and mdio signals in the gpcs mode, the 8b/10b encoding/decoding is done by the ixf1002, which enables connection of serializer/deserializer (serdes) devices implementing de/serialization and clock recovery for the 1000base-sx, 1000base-lx or 1000base-cx standards. the gpcs port is multiplexed together with the gmii port. intel ? ixf1002 dual port gigabit ethernet controller 78 datasheet 6.2 gmii port interface in the gmii mode (port_mode intel ? ixf1002 dual port gigabit ethernet controller datasheet 79 6.3 mac frame format ethernet is the generic name for the network type implementing the ieee 802.3 standard. an ethernet frame has a minimum length of 64 bytes and a maximum length of 1518 bytes, excluding the preamble and the sfd bytes. an ethernet frame format consists of the following fields: preamble start frame delimiter (sfd) two address fields length or type field data field frame check sequence (crc value) figure 17 shows the mac frame format. note: numbers in parentheses indicate field length in bytes. vlan tagged mac frames contain an additional 4 byte qtag prefix field, as described in section 4.2.2 . table 12 describes the ethernet frame fields. the crc polynomial, as specified in the 802.3 standard, is as follows: fcs(x) = x 31 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x 1 +1 the 32 bits of the crc value are placed in the fcs field so that the x31 term is the right-most bit of the first octet. the crc bits are thus transmitted in the following order: x31, x30,..., x1, x0. a frame octet is transferred on the serial line from the lsb to the msb. figure 17. mac frame format a5469-01 preamble (7) (1) (6) (6) (2) (46..1500) (4) destination address source address length/ type data+ padding sfd fcs table 12. ethernet frame description field description preamble a 7-byte field of alternating 1s and 0s: 10101010. start frame delimiter (sfd) a single-byte field containing the value 10101011. destination address a 6-byte field containing either a specific station address, or the broadcast address, or a multicast (logical) address, all of which indicate the frame ? s destination. source address a 6-byte field containing the specific station address of frame origin. length/type a 2-byte field indicating whether the frame is in the ieee 802.3 format or the ethernet format. a field greater than 1500 is interpreted as a type field, which defines the protocol type. a field smaller than or equal to 1500 (05-dc) is interpreted as a length field, indicating the number of data bytes in the frame. data+padding a data field consisting of 0 to 1500 information bytes. this data field is fully transparent because any arbitrary sequence of bits can occur. a data field shorter than 46 bytes, specified by the length field, is allowed. in its default mode, padding is enabled and up to 46 bytes are added to the data field by the ixf1002 when transmitting. frame check sequence (fcs) a 32-bit cyclic redundancy check (crc), computed as a function of the destination address field, source address field, type field, and data field. the fcs is appended to each transmitted frame and is used during reception to determine if the received frame is valid. intel ? ixf1002 dual port gigabit ethernet controller 80 datasheet 6.4 mac transmit operation this section describes the transmit operation in detail, as supported by the ixf1002. transmit activities are registered into the network management registers, which are accessible through the cpu port. 6.4.1 transmit initiation after the transmit fifo is adequately filled up to the programmed threshold level (tx_tshd intel ? ixf1002 dual port gigabit ethernet controller datasheet 81 underflow transmit data is not ready when needed for transmission. the packet is terminated on the network with a bad crc and transmit error generation (terr assertion in gmii mode, or symbol error in gpcs mode). 6.4.5 flow control the ixf1002 supports the standard flow control defined in the ieee 802.3 standard, enabling the stopping of remote node transmissions. upon triggering, the ixf1002 sends a flow-control frame in the following format: the source address field (ea1 ? ea6) is taken from the mac_add register. the ixf1002 supports all combinations of symmetric or asymmetric flow-control function. upon assertion of the flct_{i} signal or setting of the flow-control trigger bit (ser_com intel ? ixf1002 dual port gigabit ethernet controller 82 datasheet 6.5 mac receive operation this section describes the detailed receive operation as supported by the ixf1002. receive activities are registered into network management registers, which are accessible through the cpu port. 6.5.1 receive initiation the ixf1002 continuously monitors the network when reception is enabled. when an activity is recognized, the ixf1002 starts to process the incoming data. in the gmii mode, the ixf1002 detects activity when the data valid signal (dv{i}) asserts. in gpcs mode, the ixf1002 detects activity when the /s/ symbol appears. after detecting receive activity on the line, the ixf1002 starts to process the preamble bytes. 6.5.2 preamble processing the ieee 802.3 standard allows a maximum size of 56 bits (7 bytes) for the preamble, while the ixf1002 allows any arbitrary preamble length. the ixf1002 checks for the start frame delimiter (sfd) byte. if the next byte of the preamble which is different from 1010 1010, is not 1010 1011, the frame will be discarded. in this case the ixf1002 waits until the network activity stops before monitoring the network activity for a new preamble. the interpacket gap (ipg) between received frames should be at least 80-bit time. 6.5.3 frame decapsulation while the frame is being assembled, the ixf1002 continues to monitor the line condition. in the gmii mode, the ixf1002 detects the end of frame when the data valid signal (dv{i}) deasserts. in gpcs mode, the ixf1002 detects the end of the frame when the /t/ symbol appears. reception terminates with a frame error if the frame is not a valid mac frame (e.g. short, too long, no sfd), or if a receive error was detected during frame reception. in the gmii mode, receive error is detected when the receive error signal (rerr{i}) asserts during frame reception. in gpcs mode, receive error is detected when a symbol error is detected. the ixf1002 refers to the last 4 bytes received as the crc. it checks the crc bytes of all received frames and reports all errors. 6.5.4 terminating reception when reception terminates, the ixf1002 determines the status of the received frame and loads the status into the receive fifo. the ixf1002 can report the following events at the end of frame reception: overflow the ixf1002 receive fifo is not emptied as rapidly as it is filled, and the frame data is lost. if the fifo is already full when a new frame is received, it will not be loaded in the fifo and the whole packet is lost. intel ? ixf1002 dual port gigabit ethernet controller datasheet 83 ? crc error the 32-bit crc, received with the frame, did not match the crc calculated upon reception. receive error an receive error was detected during frame reception. frame too short a frame containing less than 64 bytes (including crc) was received. frame too long a frame containing more than the programmed maximum size (in pkt_max_size register) was received. 6.5.5 flow control the ixf1002 identifies standard flow-control frames during reception. if a flow-control frame is received and flow-control mode is enabled (tx_rx_param intel ? ixf1002 dual port gigabit ethernet controller 84 datasheet in gpcs mode, the transmitted packets pass through the gpcs encoding and decoding logic, and the txd<7:0> signals are unpredictable. 6.6.2 external loopback mode the external loopback mode enables verification that the logic up to the wire operates correctly. in gpsc mode, when setting the external loopback mode (mii_ctl intel ? ixf1002 dual port gigabit ethernet controller datasheet 85 when operating in the gpcs mode, the ixf1002 encapsulates and decapsulates the frames according to the ieee 802.3z 1000base-x standard. during transmit, encapsulation is performed according to the following rules: the first byte of the preamble in the mac frame is replaced with the /s/ symbol. all of the mac frame data is encoded according to 8b/10b standard encoding. after the fcs byte of the mac frame, the /t/r/r/ or /t/r/ symbol is inserted. an idle symbol /i/, is transmitted between frames. transmit error generation is translated to illegal symbol generation. during receive, decapsulation is performed according to the following rules: an /i/s/ symbol sequence will cause the internal data valid signal to be asserted (start of receive activity). the /s/ symbol is replaced by a preamble byte. all of the data symbol stream is decoded according to 10b/8b standard decoding. the /t/r/r/ or/t/r/ symbol sequence will cause the internal data valid signal to be deasserted (end of receive activity). during receive, the ixf1002 expects the frame to start with the symbol sequence /i/s/ followed by the preamble. if an /i/s/ symbol sequence is not detected, the reception of the current frame is aborted (not received), and the ixf1002 waits until the network activity stops before monitoring the network activity for a new frame. during reception, the ixf1002 also checks symbol validity. if an invalid symbol is being received, or if the frame does not end with the /t/r/r/ or /t/r/ symbol sequence, the ixf1002 reports a receive error. ewrap_{i} ewrap o enable warp. when asserted to the phy, it should loop the transmit serialized data to the receive section. this pin is controlled in the gmii management control register (mii_ctl intel ? ixf1002 dual port gigabit ethernet controller 86 datasheet 6.7.1 synchronization the ixf1002 implements the synchronization process as defined in ieee 802.3z. the synchronization process is responsible for determining whether the underlying receive channel is ready for operation. every set of ten bits transferred onto the line are called a code-group. ordered set consist of either one, two, or four code-groups where the first code-group is a special code-group. the seven bit comma string is defined as either b ? xxx0011111 ? (comma+) or b ? xxx1100000 ? (comma-). code-group synchronization is acquired by the detection of three ordered sets, containing comma strings in their first code group without receiving invalid code-group errors in between these three ordered sets. 6.7.1.1 comma detect when the physical medium attachment (pma) sublayer, which is a part of the phy, detects a comma within the incoming rx_bit stream, it may realign its current code-group boundary to that of the received comma. during reception of a comma, the comdet_{i} signal is asserted by the phy. detection of a comma is done by the phy only when the encdet_{i} signal is asserted. assertion of port_mode intel ? ixf1002 dual port gigabit ethernet controller datasheet 87 7.0 timing diagrams this section contains the ix bus port and gmii/gpcs port timing diagrams. note: the signal naming below refers to the full-64 ix bus mode. signal names should be changed in accordance to the bus mode as described in section 4.1.1.1 . 7.1 ix bus port timing diagrams this section describes the ix bus port timing diagrams. 7.1.1 transmit start-of-packet timing figure 18 shows the transmit start-of-packet timing. figure 18. transmit start-of-packet timing a4922-01 fbe_l[7:0] clk port number d1 d2 d3 d4 d5 d6 d7 port number txsel_l fps fdat[63:0] sop txasis/txerr eop be1 be2 be3 be4 be5 be6 be7 intel ? ixf1002 dual port gigabit ethernet controller 88 datasheet 7.1.2 transmit end-of-packet timing figure 19 shows the transmit end-of-packet timing. 7.1.3 transmit packet timing in split mode figure 20 shows the transmit packet timing in the split mode. figure 19. transmit end-of-packet timing a4923-02 fbe_l[7:0] clk port number d1 d2 d3 d4 d5 d6 d7 d8 txsel_l fps fdat[63:0] sop txasis/txerr eop be1 be2 be3 be4 be5 be6 be7 be8 figure 20. transmit packet timing in split mode fbe_l[7:4] clk port number d1 d2 d3 d4 d5 d6 d d txsel_l fps_txf fdat[63:32] sop_txf eop_txf be1 be2 be3 be4 be5 be6 be be intel ? ixf1002 dual port gigabit ethernet controller datasheet 89 7.1.4 transmit packet with vlan tag append timing figure 21 shows the transmit packet with vlan tag append timing figure 21. transmit packet with vlan tag append timing a4925-02 fbe_l[7:0] clk port number port number tag d1 d2 d3 d4 d5 d6 d7 txsel_l fps vtg fdat[63:0] sop txasis/txerr eop be1 be2 be3 be4 be5 be6 be7 intel ? ixf1002 dual port gigabit ethernet controller 90 datasheet 7.1.5 vlan strip mode timing figure 22 shows the transmit packet with vlan tag strip timing figure 22. transmit packet with vlan tag strip timing a4926-02 fbe_l[7:0] clk port number port number d1 d2 d3 d4 d5 d6 d7 txsel_l fps vtg fdat[63:0] sop txasis/txerr eop be1 be2 be3 be4 be5 be6 be7 intel ? ixf1002 dual port gigabit ethernet controller datasheet 91 7.1.6 transmit packet with vlan tag replace timing figure 23 shows the transmit packet with vlan tag replace timing figure 23. transmit packet with vlan tag replace timing a4927-02 fbe_l[7:0] clk port number port number d1 tag d2 d3 d4 d5 d6 d7 txsel_l fps vtg fdat[63:0] sop txasis/txerr eop be1 be2 be3 be4 be5 be6 be7 intel ? ixf1002 dual port gigabit ethernet controller 92 datasheet 7.1.7 vlan tag append in two txsel_l bursts figure 24 shows the vlan tag append in two txsel_l bursts timing. figure 24. vlan tag append in two txsel_l bursts timing a4928-03 fbe_l[7:0] clk port number port number port number d1 tag d2 d3 d4 d5 d6 d7 txsel_l fps vtg fdat[63:0] sop eop be1 be2 be3 be4 be5 be6 be7 txasis/txerr intel ? ixf1002 dual port gigabit ethernet controller datasheet 93 7.1.8 vlan tag replace in two txsel_l bursts figure 25 shows the vlan tag replace in two txsel_l bursts timing. 7.1.9 transmit fifo control timing figure 26 shows the transmit fifo control timing. figure 25. vlan tag replace in two txsel_l bursts timing a4929-02 fbe_l[7:0] clk port number port number port number d1 tag d2 d3 d4 d5 d6 d7 txsel_l fps vtg fdat[63:0] sop txasis/txerr eop be1 be2 be3 be4 be5 be6 be7 figure 26. transmit fifo control timing a4930-01 clk valid valid txctl_l txrdy{i} intel ? ixf1002 dual port gigabit ethernet controller 94 datasheet 7.1.10 transmit txrdy timing figure 27 shows the transmit txrdy timing. 7.1.11 receive start-of-packet timing figure 28 shows receive start-of-packet timing. note: rxsel_l must be deasserted for at least two cycles between two accesses to the same port. figure 27. transmit txrdy timing a4931-01 clk port number n txctl_l txrdy{i} txsel_l fps figure 28. receive start-of-packet timing a4932-01 sop clk port number port number d1 d2 d5 d6 d3 d4 rxsel_l fps fdat[63:0] fbe_l[7:0] eop rxkep rxabt rxfail 00 00 00 00 00 00 intel ? ixf1002 dual port gigabit ethernet controller datasheet 95 7.1.12 receive end-of-packet timing figure 29 shows the receive end-of-packet timing. figure 29. receive end-of-packet timing a4933-02 sop clk port number d1 d2 d3 d4 d5 status xx rxsel_l fps fdat[63:0] fbe_l[7:0] eop rxkep rxabt rxfail 00 00 00 00 00 xx ff intel ? ixf1002 dual port gigabit ethernet controller 96 datasheet 7.1.13 receive packet timing in split mode figure 30 shows the receive packet timing in the split mode. figure 30. receive packet timing in split mode a4934-02 sop_rxf clk port number d1 d2 d3 d4 d5 d6 d d status xx rxsel_l fps_rxf fdat[31:0] fbe_l[3:0] eop_rxf 00 00 00 00 00 00 00 00 xx ff intel ? ixf1002 dual port gigabit ethernet controller datasheet 97 7.1.14 receive rxfail timing figure 31 shows the receive rxfail timing. figure 31. receive rxfail timing b0022-01 sop clk port number d1 d2 d3 xx xx xx rxsel_l fps fdat[63:0] fbe_l[7:0] eop rxkep rxabt rxfail 00 00 00 ff ff ff intel ? ixf1002 dual port gigabit ethernet controller 98 datasheet 7.1.15 receive rxabt timing figure 32 shows the receive rxabt timing. figure 32. receive rxabt timing a4936-01 sop clk port number d1 d2 d3 d4 d5 rxsel_l fps fdat[63:0] fbe_l[7:0] eop rxkep rxabt rxfail 00 00 00 00 00 intel ? ixf1002 dual port gigabit ethernet controller datasheet 99 7.1.16 receive rxkep timing figure 33 shows the receive rxkep timing. figure 33. receive rxkep timing a4937-01 sop clk port number port number d1 d2 d3 d4 d5 rxsel_l fps fdat[63:0] fbe_l[7:0] eop rxkep rxabt rxfail 00 00 00 00 00 d4 00 intel ? ixf1002 dual port gigabit ethernet controller 100 datasheet 7.1.17 receive header replay timing figure 34 shows the receive header replay timing (for 20 byte header, be=f0h). 7.1.18 receive fifo control timing figure 35 shows the receive fifo control timing. figure 34. receive header replay timing a4938-01 sop clk port number port number d1 d2 d3 xx d2 rxsel_l fps fdat[63:0] fbe_l[7:0] eop rxkep rxabt rxfail 00 00 be ff 00 d1 00 figure 35. receive fifo control timing a4939-02 clk valid valid rxctl_l rxrdy{i} intel ? ixf1002 dual port gigabit ethernet controller datasheet 101 7.1.19 receive rxrdy control timing figure 36 shows the receive rxrdy control timing. 7.1.20 consecutive transmit-transmit timing figure 37 shows the consecutive transmit-transmit timing. figure 36. receive rxrdy timing a4940-03 clk rxctl_l rxrdy(i) fps(2:0) rxsel_l port number figure 37. consecutive transmit-transmit timing a4941-01 clk tx port number n dn1 dn2 dn3 dn4 dm1 dm2 dm3 tx port number m txsel_l fps fbe_l[7:0] fdat[63:0] bn1 bn2 bn3 bn4 bm1 bm2 bm3 intel ? ixf1002 dual port gigabit ethernet controller 102 datasheet 7.1.21 consecutive transmit-receive timing figure 38 shows the consecutive transmit-receive timing. 7.1.22 consecutive receive-transmit timing figure 39 shows the consecutive receive-transmit timing. figure 38. consecutive transmit-receive timing a4942-01 clk tx port number n dn1 dn2 dn3 dn4 dm1 dm2 dm3 dm4 rx port number m txsel_l rxsel_l fps fbe_l[7:0] fdat[63:0] bn1 bn2 bn3 bn4 00 00 00 00 figure 39. consecutive receive-transmit timing a4943-01 clk rx port number n dn1 dn2 dn3 dn4 dm1 dm2 dm3 tx port number m rxsel_l txsel_l fps fbe_l[7:0] fdat[63:0] 00 00 00 00 bm1 bm2 bm3 intel ? ixf1002 dual port gigabit ethernet controller datasheet 103 7.1.23 consecutive receive-receive timing figure 40 shows the consecutive receive-receive timing. 7.2 gmii/gpcs port timing diagrams this section shows the gmii/gpcs port timing diagrams. the gmii/gpcs port timing specification is compliant with the ieee 802.3 standard. 7.2.1 packet transmission timing figure 41 shows the packet transmission timing. figure 40. consecutive receive-receive timing a4944-01 clk rx port number n dn1 dn2 dn3 dn4 dm1 dm2 dm3 rx port number m rxsel_l fps fbe_l[7:0] fdat[63:0] 00 00 00 00 00 00 00 figure 41. packet transmission timing a4945-02 tclk ten txd[7:0] terr pre pre pre pre pre pre fcs fcs fcs fcs intel ? ixf1002 dual port gigabit ethernet controller 104 datasheet 7.2.2 packet reception timing figure 42 shows the packet reception timing. 7.2.3 false carrier timing figure 43 shows the false carrier timing. figure 42. packet reception timing a4946-01 rclk dv rxd[7:0] rerr pre pre sfd fcs fcs fcs fcs figure 43. false carrier timing a4947-01 rclk dv rxd[7:0] rerr 0eh xx xx xx xx xx xx xx xx xx xx xx xx xx intel ? ixf1002 dual port gigabit ethernet controller datasheet 105 8.0 electrical and environmental specifications this section contains the electrical and environmental specifications for the ixf1002. the ixf1002 supports both 5 v and 3.3 v signaling environments. 8.1 functional operating range table 15 lists the functional operating range. refer to section 8.2 for details about the absolute maximum ratings. 8.2 absolute maximum rating applying stresses beyond the absolute maximum may cause unrecoverable damage to the device. operation of this product is not implied for any condition beyond the ranges specified in the functional operation range described in section 8.1 . operating this product at the absolute maximum rating for a prolonged period can negatively impact device reliability. table 16 lists the absolute maximum ratings for the ixf1002. table 15. functional operating range parameter minimum maximum power supply (vdd) 3 v 3.6 v vdd_clmp (5.0 v signaling) ? 5v vdd_clmp (3.3 v signaling) 3 v min. [3.6 v, (vdd + 0.3 v)] esd protection voltage ? 2000 v human body model (hbm) table 16. absolute maximum rating parameter maximum rating supply voltage (vdd) 3.9 v signal pins (vsig) 5.5 v junction temperature, commercial (tj) 125 c junction temperature, extended (tj) 110 c intel ? ixf1002 dual port gigabit ethernet controller 106 datasheet 8.3 supply current and power dissipation the values listed in table 17 are based on a 80-mhz ix bus clock frequency. 8.4 temperature limit ratings table 18 lists the temperature limit ratings. 8.5 reset specification the ixf1002 reset signal (reset_l) is an asynchronous signal that must be active for at least 10 ix bus clock (clk) cycles with stable power. 8.6 fifo port specifications this section describes the fifo port specifications. 8.6.1 clock specification figure 44 shows the ix bus clock timing diagram. figure 19 lists the specifications of the ix bus clock. table 17. supply current and power dissipation power supply maximum power 3.6 v 3.6 w table 18. temperature limit ratings parameter minimum maximum storage temperature ? 55 c 125 c operating temperature, commercial 0 c70 c operating temperature, extended ? 40 c85 c figure 44. ix bus clock timing diagram a4948-01 vh vl tc vptp tl th clk intel ? ixf1002 dual port gigabit ethernet controller datasheet 107 8.6.2 3 volt dc specifications table 20 lists the dc parameters for the ix bus 3.3 v signaling levels. table 19. ix bus clock timing specifications symbol parameter condition minimum maximum freq clock frequency ? 33 mhz 85 mhz tc c yc le ti m e ? 11.75 ns 30.3 ns th clock high time ? 5 ns ? tl clock low time ? 5 ns ? vptp clock peak to peak (0.2 vdd to 0.6 vdd) 3.3 v clock 0.4 vdd ? vh clock high threshold ix bus @ 3.3 v 2.0 v ? vl clock low threshold ix bus @ 3.3 v ? 0.9 v vptp clock peak to peak (0.4 v to 2.4 v) ix bus @ 5 v 2 v ? vh clock high threshold ix bus @ 5 v 2 v ? vl clock low threshold ix bus @ 5 v ? 0.8 v table 20. ix bus 3.3 v signaling specifications symbol parameter condition minimum maximum vih input high voltage ? 2.0 v vdd_clmp + 0.5 v 1 1. overvoltage protection maximum is +7.1 v for 11 ns, through a 29 ? resistor. vil input low voltage ?? 0.5 v 2 2. undervoltage protection maximum is -3.5 v for 11 ns, through a 28 ? resistor. 0.9 v ii input leakage current 0 < vin < vdd ? 15 a 15 a voh output high voltage iout = ? 4 ma 2.7 v ? vol output low voltage iout = +4 ma ? 0.36 v cin pin capacitance ? 5 pf 10 pf intel ? ixf1002 dual port gigabit ethernet controller 108 datasheet 8.6.3 5 volt dc specifications table 21 lists the dc parameters for the ix bus 5 v signaling levels. 8.6.4 ix bus signals timing figure 45 shows the ix bus signals timing diagram. table 22 lists the timing specifications of the ix bus signals. table 21. ix bus 5 v signaling specifications symbol parameter condition minimum maximum vih input high voltage ? 2.0 v vdd_clmp + 0.5 v 1 1. overvoltage protection maximum is +11 v for 11 ns, through a 55 ? resistor. vil input low voltage ?? 0.5 v 2 2. undervoltage protection maximum is -5.5 v for 11 ns, through a 25 ? resistor. 0.9 v ii input leakage current 0.5 v < vin < 2.7 v ? 15 a 3 3. the minimum input leakage current for cdat is -500 a. 15 a voh output high voltage iout = ? 4 ma 2.4 v ? vol output low voltage iout = +4 ma ? 0.55 v cin pin capacitance ? 5 pf 10 pf figure 45. ix bus signals timing diagram a4949-01 tval ts u t h clk outputs inputs table 22. ix bus signals timing specifications symbol parameter minimum (ns) maximum (ns) tval clock-to-signal valid delay max tval is measured with load of 10 pf 16 tsu input signal valid setup time before clock 4 ? th input signal hold time before clock, excluding flow control flct{i} 0 ? th_flct flow control input signal hold time before clock 1 ? intel ? ixf1002 dual port gigabit ethernet controller datasheet 109 8.7 cpu port specifications this section describes the cpu port electrical specifications. 8.7.1 dc specifications table 23 lists the cpu port dc specifications. 8.7.2 signals timing this section describes the timing diagram of the cpu port. 8.7.2.1 read timing figure 46 shows the cpu port read timing diagram. table 23. cpu port dc specifications symbol parameter condition minimum maximum vih input high voltage ? 2v ? vil input low voltage ?? 0.8 v voh output high voltage ioh = ? 10 ma 2.4 v ? vol output low voltage iol = 10 ma ? 0.4 v ii input leakage current ?? 15 a 1 1. the minimum input leakage current for cdat is -500 a. 15 a cin pin capacitance ? 5 pf 10 pf figure 46. cpu port read timing diagram a4950-01 tcas tcah tcrh tcrr tcdrs tcdrd tcdrh tci cadd[9:0] cps cs_l crd_l cdat[15:0] crdy_l cint{i}_l intel ? ixf1002 dual port gigabit ethernet controller 110 datasheet 8.7.2.2 write timing figure 47 shows the cpu port write timing diagram. 8.7.2.3 timing parameters table 24 lists the cpu bus clock timing parameters. figure 47. cpu port write timing diagram a4951-01 tcas tcwl tcdws tcdwd tcyd tcdwh tcwh tcah cadd[9:0] cps cs_l cwr_l cdat[15:0] crdy_l table 24. timing parameters symbol parameter minimum maximum tcas cadd<9:0>, cps, cs_l setup time 10 ns ? tcah cadd<9:0>, cps, cs_l hold time 10 ns ? tcrr crdy_l assertion to crd_l deassertion 10 ns ? tcrh crd_l high width 3 tc 1 1. tc is the ix bus clock cycle time. ? tcdrs cdat<15:0> to crdy_l setup time 10 ns ? tcdrh crd_l to cdat<15:0> hold time tc 4 tc tcdrd read cdat<15:0> driving delay 3 tc 15 tc tci crd_l to cint_l clear delay ? 6 tc tcwl cwr_l width 5 tc ? tcwh crdy_l to cwr_l hold time 2 tc ? tcdws cdat<15:0> to cwr_l setup time 10 ns ? tcdwh crdy_l to cdat<15:0> hold time 10 ns ? tcdwd write cdat<15:0> latching delay 1 tc 4 tc tcyd crdy_l width in write cycle 3 tc 5 tc trtw read crdy_l deassertion to cwr_l assertion 4 tc ? twtr write crdy_l deassertion to crd_l assertion 4 tc ? intel ? ixf1002 dual port gigabit ethernet controller datasheet 111 8.8 gmii/gpcs port specifications the gmii/gpcs port electrical specifications are compliant with the ieee 802.3z standard. 8.8.1 dc specifications table 25 lists the gmii/gpcs port dc specifications. 8.8.2 signals timing this section describes the timing diagram of the gmii/gpcs port. 8.8.2.1 clocks specifications figure 48 shows the gmii port clocks timing diagram. figure 49 shows the gpcs port clocks timing diagram. figure 50 shows the gpcs receive clock timing diagram. table 25. gmii/gpcs port dc specifications symbol parameter condition minimum maximum vih input high voltage ? 2 v ? vil input low voltage ? -0.5 v 0.8 v voh output high voltage ioh = ? 10 ma 2.1 v 3.6 v vol output low voltage iol = 10 ma 0 v 0.5 v ii input leakage current ?? 15 a 15 a cin pin capacitance ? 5 pf 10 pf figure 48. gmii clock timing diagram a4952-01 vmh vml tmc tml tmh tclk gtxclk rclk figure 49. gpcs transmit clock timing diagram a4953-01 vmh vml tmc tml tmh pmatclk intel ? ixf1002 dual port gigabit ethernet controller 112 datasheet table 26 lists the gmii/gpcs port signals timing specifications. 8.8.2.2 gmii signals timing diagrams figure 51 shows the gmii port transmit timing characteristics. figure 52 shows the gpcs interface receive timing diagram. figure 50. gpcs receive clock timing diagram a4954-01 vmh vml tfreq ta-b pmarclk<1> pmarclk<0> vmh vml table 26. gmii/gpcs port signals timing specifications symbol parameter minimum maximum tmc tclk, gtxclk, rclk cycle time 8ns -100ppm 8ns +100ppm tmh tclk, gtxclk, rclk high time 0.4 tmc 0.6 tmc tml tclk, gtxclk, rclk low time 0.4 tmc 0.6 tmc vmh tclk, gtxclk, rclk high threshold 2 v ? vml tclk, gtxclk, rclk low threshold ? 0.8 v tfreq pmarclk frequency 16 ns -100ppm 16 ns +100ppm tdrift pmarclk drift rate 0.2 s/mhz ? tduty pmarclk duty cycle 0.4xtfreq 0.6xtfreq ta-b pmarclk skew 7.5 ns 8.5 ns figure 51. gmii port transmit timing diagram a4955-02 tmhold tmvalid gtxclk txd ten terr figure 52. gmii port receive timing diagram a4956-01 tmsu tmh rclk rxd dv rerr intel ? ixf1002 dual port gigabit ethernet controller datasheet 113 8.8.2.3 gmii signals timing parameters table 27 describes the gmii signals timing parameters. 8.8.2.4 gpcs signals timing diagrams figure 53 shows the gpcs port transmit timing characteristics. figure 54 shows the gpcs interface receive timing diagram. table 27. signals timing parameters symbol parameter minimum maximum tmhold txd, terr, ten, output valid hold after rise of gtxclk 1.5 ns ? tmvalid gtxclk to output valid delay ? 5 ns tmsu input setup time before rise of rclk 2 ns ? tmh input hold time after rise of rclk 0 ns ? figure 53. gpcs port transmit timing diagram a4957-02 tgvalid tghold pmatclk txd ten terr figure 54. gpcs receive timing diagram a4958-02 thold tsetup thold tsetup comma code-group valid data rclk rxd[9:0] comdet pmarclk<0> intel ? ixf1002 dual port gigabit ethernet controller 114 datasheet 8.8.2.5 gpcs signals timing parameters table 28 describes the gpcs signals timing parameters. 8.9 jtag port specifications this section describes the jtag port electrical specifications. 8.9.1 dc specifications table 29 lists the jtag port dc specifications. table 28. gpcs signals timing parameters symbol parameter minimum maximum tghold txd output valid hold after rise of pmatclk 1.5 ns ? tgvalid rise of pmatclk to output valid delay ? 5 ns tsetup data setup before rise of pmarclk 2 ns ? thold data hold after rise of pmarclk 0 ns ? table 29. jtag port dc specifications symbol parameter condition minimum maximum vih input high voltage ? 2v ? vil input low voltage ?? 0.8 v voh output high voltage ioh = ? 4 ma 2.4 v ? vol output low voltage iol = 4 ma ? 0.4 v ii input leakage current (tck) ?? 20 a 20 a iip input leakage current with internal pull-up (tdi, tms) ?? 1500 a 20 a io tristate output leakage current (tdo) ?? 20 a 20 a cin pin capacitance ? 5 pf 10 pf intel ? ixf1002 dual port gigabit ethernet controller datasheet 115 8.9.2 signals timing figure 55 shows the jtag port timing characteristics. table 30 lists the jtag port timing specifications. figure 55. jtag port timing diagram a4959-01 tjh tjl tjval tjc tjsu tjh tck tdo tms tdi table 30. jtag port timing specifications symbol parameter minimum maximum tjc tck cycle time 90 ns ? tjh tck high time 0.4 tjc 0.6 tjc tjl tck low time 0.4 tjc 0.6 tjc tjval tck fall to tdo valid delay ? 25 ns tjsu tms and tdi setup time before tck 20 ns ? tjh tms and tdi hold time from tck 5 ns ? intel ? ixf1002 dual port gigabit ethernet controller datasheet 117 9.0 mechanical specifications the ixf1002 is contained in a 304-esbga package. figure 56 shows the part marking. product name stepping marketing part number notes gcixf1002ed c0 832414 multi-packet mode. gcixf1002edt c0 838953 extended temperature version. figure 56. part marking a8455-02 gcixf1002xxx intel ? ixf1002 dual port gigabit ethernet controller 118 datasheet figure 57 shows the 304-esbga package and table 31 lists the dimensions in millimeters. figure 57. 304-esbga package a5472-01 23 a b c d e f g h j k l m n p r t u a a bottom view side view a-a section view e e d p s s e 1 a 1 aa 2 d 1 d e a1 ball corner seating plane b .30 aa c v w y aa ab ac 222120191817161514 12 10 8 654321 13 11 9 7 b ss bbb ccc c c aaa ddd intel ? ixf1002 dual port gigabit ethernet controller datasheet 119 table 31. 304-esbga dimensional attributes dimension symbol minimum nominal maximum package overall thickness a 1.41 1.54 1.67 ball height a1 0.56 0.63 0.70 body thickness a2 0.85 0.91 0.97 body size e 30.90 31.00 31.10 ball footprint e1 27.84 27.94 28.04 ball matrix ?? 23 23 ? number of rows deep ?? 4 ? ball diameter b 0.60 0.75 0.90 minimum distance encapsulation to balls d ? 0.6 ? ball pitch e ? 1.27 ? coplanarity aaa ?? 0.20 parallel bbb ?? 0.15 top flatness ccc ?? 0.20 seating plane clearance ddd 0.15 0.33 0.50 encapsulation height p 0.20 0.30 0.35 solder ball placement s ? ? 0.635 intel ? ixf1002 dual port gigabit ethernet controller datasheet 121 joint test action group ? test logic a this appendix describes the joint test action group (jtag) test logic and the associated registers. a.1 general description jtag test logic supports testing, observation, and modification of circuit activity during normal operation of the components. the ixf1002 supports the ieee standard 1149.1 test access port and boundary scan architecture. the ixf1002 jtag test logic allows boundary scan to be used to test both the device and the board it is installed in. the jtag test logic consists of the following four signals to serially interface within the ixf1002: tck ? jtag clock tdi ? test data and instructions in tdo ? test data and instructions out tms ? test mode select note: if jtag test logic is not used, the tck pin should be connected to ? 0 ? , and both the tms and tdi pins should be connected to ? 1 ? . the tdo signal should remain unconnected. note: if jtag logic is used, a 1149.1 ring is created by connecting one device ? s tdo pin to another device ? s tdi pin and so on, to create a serial chain of devices. in this application, the ixf1002 receives the same tck and tms signals as the other devices. the entire 1149.1 ring is connected to either a motherboard test connector for test purposes or to a resident 1149.1 controller. a.1.1 test access port controller the test access port (tap) controller interprets ieee p1149.1 protocols received on the tms pin. the tap controller generates clocks and control signals to control the operation of the test logic. the tap controller consists of a state machine and a control dispatch logic. the ixf1002 fully implements the tap state machine as described in the ieee p1149.1 standard. a.2 registers in jtag test logic, three registers are implemented in the ixf1002: instruction register bypass register boundary-scan register intel ? ixf1002 dual port gigabit ethernet controller 122 datasheet a.2.1 instruction register the ixf1002 jtag test logic instruction register is a 3-bit scan-type register that is used to program the jtag machine to the appropriate operating mode. its contents are interpreted as test instructions. table a-1 lists the instructions register. a.2.2 bypass register the bypass register is a 1-bit shift register that provides a single-bit serial connection between the tdi and tdo signals. this register is used when the instruction register is set to bypass mode or after powerup. a.2.3 boundary-scan register the boundary-scan register consists of cells located on all the pads. this register provides the ability to perform board-level interconnection tests by shifting data inside through tdi and outside through tdo. it also provides additional control and observation of the ixf1002 pins. for example, the ixf1002 boundary-scan register can observe the output enable control signals of the i/o pads. table a-1. instructions register ir<2> ir<1> ir<0> description 000 extest mode (mandatory instruction) . test data is shifted into the ixf1002 boundary-scan register and then transferred in parallel to the output pins. 001 sample-preload mode (mandatory instruction) . test data is loaded in parallel from the input pins into the ixf1002 boundary-scan register and then shifted out for examination. 0 1 0 reserved 0 1 1 reserved 1 0 0 reserved 101 tristate mode (optional instruction) . allows the ixf1002 to enter the power-saving mode. in this mode, all the port pads are tristated. 110 continuity mode (optional instruction) . allows the ixf1002 continuity test. in this mode, all the port pads get a ? 0 ? value. 111 bypass mode (mandatory instruction) . allows the test features on the ixf1002 test logic to be bypassed. bypass mode is selected automatically when power is applied. intel ? ixf1002 dual port gigabit ethernet controller datasheet 123 glossary b b.1 list of abbreviations 1000base-x 802.3z phy specification for 100mb/s 2 optical fibers or 2 pairs of specialized balanced cabling. 802.3 ieee csma/cd lan standard (ethernet) esbga ball grid array package mb/s mega bits per second mhz mega hertz cpu central processing unit crc cyclic redundancy check appended to ethernet packets fifo first in first out memory ieee institute of electrical and electronics engineers, inc. ip internet protocol ipg interpacket gap jtag join test action group lan local area network mac media access control od open drain sfd start frame delimiter gmii gigabit media independent interface gpcs gigabit physical coding sublayer phy physical layer entity rmon remote network monitoring management snmp simple network management protocol vlan virtual bridged lan wan wide area network intel ? ixf1002 dual port gigabit ethernet controller datasheet 125 multi-packet mode c c.1 overview this addendum contains the description of a new multi-packet mode of operation introduced for the ixf1002 dual port gigabit ethernet controller (gcixf1002ed only). c.2 introduction - txrdy assertion/deassertion rules the ixf1002 uses a generic bus interface (ix bus) for data transfer to and from its fifos. the transmit fifo (tfifo) is accessed according to a port selection signal (fps) as well as a transmit enabling signal (txsel_l). when a data transfer occurs, it is synchronized to the main clock (clk), and new data may be sent on each clock cycle. the ixf1002 provides a dedicated signal (txrdy), which indicates that it is ready for data transfer into the tfifo. the ixf1002 asserts the txrdy signal when both of the following criteria are met: the amount of free space in the tfifo is greater than the predetermined fifo transmit threshold (ffo_tshd intel ? ixf1002 dual port gigabit ethernet controller 126 datasheet note that when the ixf1002 is not in multi-packet mode, the device retains all of the features as described in the ixf1002 data sheet. c.3 multi-packet mode in order to enable systems that require a high serial transmit threshold to reach full wire speed operation, multi-packet mode was introduced. when this mode is enabled (port_mode<14:13> = 1), up to 16 full packets may be stored in the ixf1002 ? s tfifo. in multi-packet mode, txrdy signal deassertion rules are changed to indicate at least one of the following: the amount of free space in the tfifo is below the fifo transmit threshold (ffo_tshd intel ? ixf1002 dual port gigabit ethernet controller datasheet 127 bit name bit # bit description ? 15 reserved ? 14 reserved should be written to 0 for future compability. mltpkt 13 multi-packet mode. when set, the device operates in multi-packet mode. while working in multi-packet mode, the txrdy signal is deasserted when at least one of the following is true: the amount of free space in its tfifo is below the fifo transmit threshold. the number of full packets stored in the tfifo is sixteen. a data burst on the ix bus is in progress. note that the single packet mode control bit (tx_rx_param intel ? ixf1002 dual port gigabit ethernet controller 128 datasheet lcke 7 enable activation of lock to reference signal. when set, the lckref_{i} signal will be asserted to the phy when there is no activity (no signal detected) on the line. used only in gpcs mode. fxecd 6 fix enable comma detect signal. when set, the encdet_{i} signal to the phy will be continuously asserted. when cleared, the encdet_{i} signal will be asserted only during loss of synchronization. used only in gpcs mode. ilpk 5 internal loopback mode. when set, the port is disconnected from the line and all the transmitted packets are sent back to the receive side. packets are not transmitted onto the line and packets received from the line are rejected. ? 4:3 reserved cpubw 2 cpu data bus width. when asserted, bus width is 16, all cdat<15:0> bits are in use. when deasserted, bus width is 8, indicating that the 8 low bits cdat<7:0> are in use. sddis 1 signal detect disable. setting this bit will cause ixf1002 to consider the value of the sd{i} input signal as high, regardless to the actual value on the pin. used only in gpcs mode. gpcs 0 gpcs port mode. this bit defines the gmii/gpcs port mode. if a gpcs phy device is connected, this bit must be set. if a gmii phy device is connected, this bit must be reset. access rules register access r/w value after reset 0000h bit name bit # bit description |
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